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TM4C1294KCPDT: How to set USB BULK TX ring buffer to start at 0

Anthony Levine1
Prodigy 130 points
Part Number: TM4C1294KCPDT

For USB BULK mode; how do I reset the TX ring buffer to zero?  It seems to always have a random starting point (even after flush-tx-buffer).

My issue to to not have to check for end-of-buffer-wrap after each entry, and so maximise throughput for a certain block.

Thanks,

Anthony Levine

  • 0
    TI__Guru*** 135355 points
    Hello Anthony,

    It doesn't look like such a feature is included in TivaWare USB Library, you are free to implement that on your end if you wish in the application layer. Should just involve clearing the ui32WriteIndex and ui32ReadIndex after a flush at first glance.

    Regarding maximizing throughput, you may find the following useful: e2e.ti.com/.../1535533
  • 0 in reply to Ralph Jacobi
    Prodigy 130 points
    No easy way to start with sTxRing.ui32WriteIndex = 0 or any low number.
    i.e.
    USBBufferInfoGet(&g_sTxBuffer, &sTxRing);
    ui32WriteIndex = sTxRing.ui32WriteIndex;

    Tried FlushBuffers and setting sTxRing.ui32WriteIndex = 0, but when you reread sTxRing.ui32WriteIndex, it is always at some other number.
  • 0 in reply to Anthony Levine1
    TI__Guru*** 135355 points
    Hello Anthony,

    As I didn't write the USB library I am not sure what is causing that method to reset the buffer pointer to zero to not work as we expect. I reviewed the relevant files for driverlib and usblib and I don't see anything that stands out to me which would be preventing writing the sTxRing.ui32WriteIndex to zero. Unfortunately from what I can see no one else has had this requirement before, so I don't have any reference to go on as far as other ideas, so all I can think of is to use CCS breakpoints and see if:

    A) Does the ui32WriteIndex accept the value of zero within variable view
    B) If yes, then does it change at a specific point that it shouldn't, and what API causes the change?

    Also, based on my searching of similar inquiries, I think discussions about maximizing throughput like the one I posted above suggest that the real bottleneck from the ring buffer is more from the size of the buffer and state machines, so I am suspicious that this topic never came up because it isn't really the right solution for improving throughput.