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TM4C1294KCPDT: GPTM PWM match count load via CCP event interrupt issue

Guru 55913 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: REF2033, LM94022

Having issue where suddenly without warning a lower value match count loaded via the CCP0 event interrupt jams the down count match value register retrieval via the GPTM counting architecture.

When that occurs it suddenly shifts the PWM duty cycle from 50% to 100% and no further match count loads are possible. Double clearing interrupt handlers source or setting the CCP0 interrupt event edge mode differently has no effect to stop jamming the GPTM match value register.

Notably this issue seems to occur relative ADC1 temperature sensor erratum #09 which no level of NHs encoding can stop from occurring. Lower 2 digit values of MCU temperatures change to a very high 32 bit random count then return to the lower decimal value. Hence an MCU temperature alarm might falsely occur if (>) is used to detect a fault temperature value yet (=) seems the WA to stop false trips when ADC #09 occurs.

  • Not sure what you are trying to convey but if the period is less than the duty cycle, what you observed is to be expected.

    Maybe you want to restate your problem?

  • I just noticed the posters name. Is it possible that this problem is linked to your fractional integer trouble in another thread?
  • Hi BP101,

    I'm not clear with your question. Are you trying to change the match register in the middle while the counter is counting down? What are in GPTMTxILR and GPTMTxPR registers and what was in the original match register in GPTMTxMATCHR and what was later changed to? Is it possible that you try to change the match register to a larger value after the counter has already passed it. For example, the period is set to 100 and the match is set to 50. While the counter is down counting and the current counter value is 60, you try to change to a value of 70. Since the counter has already passed the 70 you will see a 100% duty cycle on the PWM. This is one possibility. In the datasheet there is a diagram that shows when the match register is larger than the interval load register the the PWM will stay 100% duty cycle indefinitely.
  • Hi Charles,

    Seemingly a GPTM count down of 60 and match loading 70 should load any new value on the next 0 count or time out which ever it is set for.

    It would seem disabling the CCP0 event edge interrupt and moving CCP0 handlers match count via HWREG() load code into another GPTM handler is a work around. Perhaps there was a timing issue with CCP0 NVIC interrupt being used to load his own match value at 40us intervals. CCPO interrupted match loads worked for 10 minutes before pegging the match count to 100% duty.

    Also seeing ADC1 SS1 (Nhs 0x4444) producing random 10*C jumps in the GPTM match load values. The two sequencer steps for sensors LM94022 rapidly changes PWM duty cycle matching fan speed relative. ADC0/1 are using VREFA+ via REF2033 pin 2 AGND and MCU pin 10 GNDA tied to same AGND via 0R. Also have VREFA+ with 0.1uf/0.01uf parallel near MCU pin.

    Seemed logical to match REF2033 pin 2 AGND to that of MCU pin 10 GNDA source. PCB can easily switch GNDA pin 10 to digital ground via 0R insertions not found on the EK launch pads. Not sure yet but that GNDA source may have some effect on the ADC sample hold capacitors.
  • Hi BP101,
    Is it possible that the event interrupt is somehow synchronous to the PWM? Let's say your event interrupt is always synchronous to the counter value at 10. If you try to change the match value to anything greater than 10 it will not work as the counter has already passed those higher values. If you want to change the match value I will suggest you change based on the PWM edge (i.e. rise or fall or both) interrupt.
  • Charles Tsai said:
    If you want to change the match value I will suggest you change based on the PWM edge (i.e. rise or fall or both) interrupt.

    That is how GPTM PWM CCP0 event edge interrupt was being tested (POS/NEG/BOTH) yet somehow all edge types locked the match register at various times no matter the INT priority set. The match value should be synchronous by virtue of how it being loaded into GPTM by design.

    Moving that CCP0 interrupt handler code into another GPTM SS1 INT handler was WA or fixed GPTM Match count load timing issues. Yet GPTM match counts are still jumping relative to SS1 samples perhaps at specific AHB traffic levels.

    The random ADC0 sample count jumps leading to rapid match count duty changes remain but only when the PWM module is driving the PWM output control block. Changing INT priority of ADC1 SS1, Nhs hold time or GPTM INT priority is not stopping that jump from occurring.  The SS1 interrupt array values are static and should not be dropping sample hold but it seems that is what is occurring yet only on ADC1 SS1 samples and MCU temp SS3. Everything is fine SS1 samples of two LM94022 readings, even via static hot air source testing until PWM0 peripheral takes AHB and NVIC priority. Then LM94022 samples values randomly jump by over 10*C or more so the fan sounds like a person revving the throttle of a motor cycle engine, varoom varoom.  

    Will open another post on that issue.

  • When - and "IF" you (finally) TAME your (long reported) MISBEHAVING FAN - I will (personally) ... Notify the Smithsonian...
  • And no ideas why AHB seems to back up only when PWM generators are driving PWM output control block? Look again last post made edit to the match count load INT handler source SS1, yet another GPTM does load SS1 trigger processor in 10ms intervals. Fan motor makes random burst sounds like wind howling in a rain storm, makes real freaky sound. Both LM94022 SS1 samples seem to detect Ghosts but only when PWM GENS are outputting.
  • You Sir - drive a (very) hard bargain.    This reporter will contact the Smithsonian's "Ghost Wing" - just as you direct...

  • "AHB seems to back up"

    Are you talking about AHB the bus or AHB the canal here?