Other Parts Discussed in Thread: REF2033, LM94022
Having issue where suddenly without warning a lower value match count loaded via the CCP0 event interrupt jams the down count match value register retrieval via the GPTM counting architecture.
When that occurs it suddenly shifts the PWM duty cycle from 50% to 100% and no further match count loads are possible. Double clearing interrupt handlers source or setting the CCP0 interrupt event edge mode differently has no effect to stop jamming the GPTM match value register.
Notably this issue seems to occur relative ADC1 temperature sensor erratum #09 which no level of NHs encoding can stop from occurring. Lower 2 digit values of MCU temperatures change to a very high 32 bit random count then return to the lower decimal value. Hence an MCU temperature alarm might falsely occur if (>) is used to detect a fault temperature value yet (=) seems the WA to stop false trips when ADC #09 occurs.