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TM4C1294NCPDT: Using SSI in Advanced Bi-Mode

Part Number: TM4C1294NCPDT

I'm trying to use SSI0 to receive data from two external ADCs at the same time.

Using the SSI in advanced bi-mode (read) seems to make sense for my application.

SSI0CLK and SSI0XDATA0 (MOSI) are hooked up to both ADCs. ADC1 is hooked up to SSI0XDATA1 (MISO) and ADC2 is hooked up to SSI0XDATA2 (MISO).

Does the SSI in this mode support this kind of use case? How is the data stored in the Receive FIFO from each data line?

  • Hi Richard,
    In Advanced bi and quad-SSI mode the data transfers are only half-duplex. You seem to want a full-duplex setup using SSI0XDATA0 to transmit and using SSI0XDATA1 and SSI0DATA2 for receive. This will not work. Please refer to the datasheet for details.

    17.3.3 Advanced, Bi- and Quad- SSI Function
    Bi-SSI uses two data pins, SSInXDAT0 and SSInXDAT1, that can be configured to receive or
    transmit data. In Quad-SSI mode, SSInXDAT0, SSInXDAT1, SSInXDAT2 and SSInXDAT3 allow
    four bits of data to be received or transmitted at once. Note that in bi- and quad-SSI data transfers
    are only half-duplex.
    By programming the MODE bits in the SSICR1 register, Advanced, Bi- or Quad- SSI can be enabled.
    A direction bit, DIR, is provided to program the direction of operation during a Bi- or Quad SSItransaction.
    Since Bi- and Quad-SSI cannot be full duplex, the DIR bit defines whether or not the
    RX FIFO is disabled. In Advanced operation, if the QSSI module TX (write) mode is enabled, the
    RX FIFO is automatically prevented from receiving any data. When Advanced SSI is in RX (read)
    mode, it operates as a full-duplex interface.
  • Charles,

    I understand that this mode only works in half duplex.

    If I just read from the ADCs, how would this work?

    How does the data get transferred into the receive FIFO?
  • Hi Richard,

     You need to use the DIR bit as I earlier quotedt to change the direction of the data flow when you are in the Bi-SSI mode.

    By programming the MODE bits in the SSICR1 register, Advanced, Bi- or Quad- SSI can be enabled.

    A direction bit, DIR, is provided to program the direction of operation during a Bi- or Quad SSI transaction.

    Since Bi- and Quad-SSI cannot be full duplex, the DIR bit defines whether or not the

    RX FIFO is disabled.

  • Charles,

    The DIR bit makes sense.

    I still do not understand how the data is read from the SSI module.

    How do I read from both data pins? Data is being clocked in at the same time on both pins. How do I access this data?

    Is the RX FIFO tied to data coming in on the SSI0XDAT1 pin?
    Is the TX FIFO tied to data coming in on the SSI0XDAT2 pin?

    Is every other read to the SSI_O_DR register tie to a different data input pin.

    There doesn't seem to be a mechanism to read data from each SSI0 data line when in this mode.

    Another idea, is the data combined somehow? Is each data line treated as a separate serial input or are they treated like parallel input data lines?
  • Richard,
    The Bi or Quad-SSI mode is supposed to work with the external SPI that supports multi-I/O. There is some flash devices that support as such. Suppose you are expecting to read a data 0x55 from a slave serially, the SSI module master will provide 8 SSICLK and you will receive the binary bit 0,1,0,1,0,1,0,1. If you are in bi-mode then the SSI master will provide 4 SSICLK and in each clock you will receive two bits and they are "01", "01","01","01". Now you are trying to connect the SSI master in bi mode to two different ADCs. It will not work. These ADCs still expect the master to send 8 clocks, not four. They have no understanding that the master is serial, bi- or quad. They need 8 clocks for a 8-bit data.

    Is there any reason why you can't use two SSI modules in your application? I think you will make your project much easier.