TMS570LC4357: Power-Up Sequence - Number of oscilaltor cycles

Christopher TRITANT

Hello,

We are using the TMS570LC4357 and we have question about 6.3.1. Power-Up Sequence (Table 6-3 Power-Up Phases) in the datashet (spns195c)):

By mentioning the Table 6-3, it is described that "The device goes through the following sequential phases during power up"

Regarding the number of oscilaltor cycles described in the Table 6-3, is it the number of cycles as of the nPORRST release or the number of cycles before the nPORRST assertion or the number of cycles pending the nPORRST ?

Best regards,

Christopher

over 8 years ago

0 QJ Wang over 8 years ago

TI__Guru**** 200756 points

Hi Christopher,

The power up sequence starts with the input voltage rising above VCCIO PORH and the release of reset (nPORRST). I draw a diagram to show the relationship among VCC/VCCIO, PORRST and OSC Valid:

0 QJ Wang over 8 years ago in reply to QJ Wang

TI__Guru**** 200756 points

The "1024 OSC cycles " in my diagram should be "OSC startup time + 1024 OSC cycles".

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TMS570LC4357: Power-Up Sequence - Number of oscilaltor cycles