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RM48L952: RM48xx SPI Slave mode,

paddu2017
Expert 2885 points
Part Number: RM48L952

Hi,

Do we require to use MibSPI's CS in Slave mode?
In our application RM48L952 is used as a SPI slave 3 pins only(without CS).
We would like to know what should be taken care of in order to
implement SPI read/write with different size of data in Slave mode?

I believe in case of master mode, we can read/write with different size if we
change the group, but in this case we are not able to start the comminication
even if we change the group(except for group0).

PLease let me know do we need CS to implement this?

Best Regards
paddu

  • 0
    TI__Guru**** 197166 points
    Hello Paddu,

    If the CSHOLD bit in a buffer is set to 1, then the MibSPI does not wait for the SPICS pins to be deactivated at the end of the shift operation to copy the received data to the receive RAM. With this feature, it is possible for a slave in multi-buffer mode to do multiple data transfers without requiring the SPICS pins to be deasserted between two buffer transfers.

    If the CSHOLD bit in a buffer is cleared to 0 in a slave MibSPI, even after the shift operation is done, the MibSPI waits until the SPICS pin (if functional) is deasserted to copy the received data to the RXRAM.

    If the CSHOLD bit is maintained as 0 across all the buffers, then the slave in multi-buffer mode requires its SPICS pins to be deasserted between any two buffer transfers; otherwise, the Slave SPI will be unable to respond to the next data transfer.

    In compatibility SPI mode, the slave does not require the SPICS pin to be deasserted between two buffer transfers. The CSHOLD bit of the slave will be ignored in compatibility mode.
  • 0 in reply to QJ Wang
    Expert 2885 points

    Hi Wang,

    Thank you for the quick reply,

    I believe the above info(24.2.11.2) was added recently.

    Meanwhile, CSHOLD bit's description in the Multi-Buffer RAM Transmit Data Register (TXRAM)
    mentions that The CSHOLD bit is supported in master mode only, it is ignored in slave mode.

    Which is contradictory to your statement above.
    Could you please let me know if this is a typo in the manual?

    One more question is in case if we want to run SPI in compatibility mode,
    only MSPIENA bit should be set to 0?, please let me know if there is any other
    settings necessary.

    Best Regards
    paddu

  • 0 in reply to paddu2017
    Expert 2885 points

    Hi Wang,

    An update about this issue.

    We tried to change the CSHOLD bit to 1 as per your suggestion,but unsuccessful,
    the communication works in Group0 but no communication in Group1.

    CSHOLD bit is set in the source code as below.

    Please let me know if there is anything else to be considered.


    Best Regards
    paddu

  • 0 in reply to paddu2017
    Expert 2885 points
    Hi Wang,

    Below E2E mentions that In MIBSPI Slave mode, the CS lines are used to specify which Transfer Group,
    so is it mandatory to use CS line to read/write with different size and different group?
    e2e.ti.com/.../1012758

    Best Regards
    paddu
  • 0 in reply to paddu2017
    TI__Guru**** 197166 points
    Hello Paddu,

    When operating in slave mode, the MibSPI uses the chip-select pins to generate a trigger to the Transfer Group. However, when the MibSPI is in 3-pin or 4-pin with SPIENA mode, just one Transfer Group can be triggered and it is restricted to Transfer Group 0 (TG0).