TMS570LC4357: MIBSPI RX DMA triggers on buffers other than the last in a transfer group don't work reliably

Hello Brian,

Could you please check my example code to see if it meets your requirements? I added comments for MibSPI DMA settings, Transfer Group setting, MiSPI RAM configuration. Any questions, please let us know. The following is the code of main() function of my sample project:

/* Include Files */

#include "HL_sys_common.h"

/* USER CODE BEGIN (1) */

#include "HL_mibspi.h"

#include "HL_sys_dma.h"

#include "HL_sys_core.h"

#include "HL_sci.h"

#include "HL_reg_esm.h"

#include <stdio.h>

#include <string.h>

#define E_COUNT      1   /*Element count*/

#define F_COUNT      8   /*Frame count*/

#define D_SIZE      E_COUNT * F_COUNT

#define TG0         1

#define TG1         0

/* USER CODE END */

/** @fn void main(void)

*   @brief Application main function

*   @note This function is empty by default.

*

*   This function is called after startup.

*   The user can use this function to implement the application.

*/

/* USER CODE BEGIN (2) */

void loadDataPattern(uint32 psize, uint16* pptr, uint16 pattern);

void dmaConfigCtrlRxPacket(uint32 sadd, uint32 dadd, uint16 ElmntCnt, uint16 FrameCnt);

void dmaConfigCtrlTxPacket(uint32 sadd, uint32 dadd, uint16 ElmntCnt, uint16 FrameCnt);

/* TG start address */

uint16 tgPSTART[8];

g_dmaCTRL g_dmaCTRLPKT_RX, g_dmaCTRLPKT_TX;

#pragma SET_DATA_SECTION(".sharedRAM")

uint16 TXDATA[D_SIZE];         /* transmit buffer in sys ram, MibSPI1 TG0 */

uint16 RXDATA[D_SIZE]= {0};    /* receive  buffer in sys ram, MibSPI1 TG0 */

#pragma SET_DATA_SECTION()

uint16 tx_data1[8] = {0x5A11,0x5A22,0x5A33,0x5A44,0x5A55,0x5A66,0x5A77,0x5A88};

/* USER CODE END */

int main(void)

{

/* USER CODE BEGIN (3) */

   uint16 i;

   esmREG->SR1[0] = 0xFFFFFFFF;

   esmREG->SR1[1] = 0xFFFFFFFF;

   esmREG->SR1[2] = 0xFFFFFFFF;

   esmREG->EKR = 0x0000000A;

   esmREG->EKR = 0x00000000;

    sciInit();

    printf("hello\n");

    /*Enable RQ interrupt*/

   _enable_IRQ_interrupt_();

   /* initializing MibSPI1 and MibSPI3 - enabling tg 0 , length 127 (halcogen file)*/

   mibspiInit();

   /* Delay in between transmissions or between 2 buffer frames */

   /* The delay to be applied is equal to:  (WDELAY + 2) × PVCLK, where PVCLK is the Period of VCLK */

   /* In this example, VCLK=75MHz, PVCLK=13.33ns, the delay between 2 buffer frame is: 257*13.33=3.43us*/

   mibspiREG1->FMT0 &= (uint32)(0x00FFFFFF);  /* clear the WDELAY bits: bit 31~24 */

   mibspiREG1->FMT0 |= (uint32)(0xFF << 24);  /* add delay: 0xFF, maximum */

   /* MibSPI1: master

    * TG0: 8 buffers,

    * Oneshot transfer is set: A transfer from TG0 will be performed only once after a valid trigger event

    * Trigger event: always

    * Trigger source: disabled

    * By setting the TRIGSRC to 0, the TRIGEVT to 7h (ALWAYS), and the ONESHOTx bit to 1, software can trigger

    * this TG. Upon setting the TGENA bit, the TG is immediately triggered.

    */

   mibspiREG1->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */

                          | (uint32)((uint32)0U << 29U)  /* pcurrent reset */

                          | (uint32)((uint32)TRG_ALWAYS<< 20U)  /* trigger event */

                          | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */

                          | (uint32)((uint32)0U << 8U);  /* start buffer */

   mibspiREG1->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */

                          | (uint32)((uint32)0U << 29U)  /* pcurrent reset */

                          | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */

                          | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */

                          | (uint32)((uint32)8U << 8U);  /* start buffer */

   /* Configure the TX RAM of MibSPI1 TG0:

    * Bufmode: suspend single-transfer mode. Suspend-to-wait until the corresponding TXFULL flag is set (the sequencer stops

    *          at the current buffer until new transmit data is written in the TXDATA field).

    * Chip Select Hold: off, the chip select signal is deactivated at the end of a transfer

    * WDELAY is enabled, the delay is defined in FMT0

    * Lock transmission: disabled, any higher-priority TG can begin at the end of the current transaction

    * Data fornat: FMT0

    * Chip Select: CS0

    * */

   for (i=0; i<8; i++)

   {

       mibspiRAM1->tx[i].control = (uint16)((uint16)5U << 13U)  /* buffer mode */

                                 | (uint16)((uint16)0U << 12U)  /* chip select hold */

                                 | (uint16)((uint16)1U << 10U)  /* enable WDELAY */

                                 | (uint16)((uint16)0U << 11U)  /* lock transmission */

                                 | (uint16)((uint16)0U << 8U)  /* data format */

                                 | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */

   }

   /* MibSPI3: Slave, 1 TG

    * TG0: 1 buffer only

    * Oneshot transfer is reset: TGx initiates a transfer every time a trigger event occurs and TGENA is set.

    * In slave mode, the fields like trigger source and trigger event are not taken into account by the sequencer.

    * Only the SPICS pins can trigger a Transfer Group.

    * */

   mibspiREG3->TGCTRL[0U] = (uint32)((uint32)0U << 30U)  /* oneshot */

                          | (uint32)((uint32)0U << 29U)  /* pcurrent reset */

                          | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */

                          | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */

                          | (uint32)((uint32)0U << 8U);  /* start buffer */

   mibspiREG3->TGCTRL[1U] = (uint32)((uint32)0U << 30U)  /* oneshot */

                          | (uint32)((uint32)0U << 29U)  /* pcurrent reset */

                          | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */

                          | (uint32)((uint32)TRG_DISABLED << 16)  /* trigger source */

                          | (uint32)((uint32)1U << 8U);  /* start buffer */

   /* Configure the TX RAM of MibSPI1 TG0:

    * Bufmode: suspend overwrite-protect mode. Suspend-to-wait until the corresponding RXEMPTY flag is set

    *          (the sequencer stops at the current buffer until the previously-received data is read by the host.)

    * Chip Select Hold: 0. If the CSHOLD bit in a buffer is cleared to 0 in a slave MibSPI, even after the shift operation is done,

    * the MibSPI waits until the SPICS pin is deasserted to copy the received data to the RXRAM.

    * If the CSHOLD bit is maintained as 0 across all the buffers, then the slave in multi-buffer mode requires its

    * SPICS pins to be deasserted between any two buffer transfers; otherwise, the Slave SPI will be unable to

    * respond to the next data transfer.

    * Data fornat: FMT0

    * Chip Select: CS0

    * */

   for(i=0; i<1; i++){

        mibspiRAM3->tx[i].control = (uint16)((uint16)6U << 13U)  /* buffer mode */

                                  | (uint16)((uint16)0U << 12U) /* chip select hold */

                                  | (uint16)((uint16)0U << 10U)  /* enable WDELAY */

                                  | (uint16)((uint16)0U << 8U)  /* data format */

                                  | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */

  }

#if 0

   /* TG start address. PSTARTx stores the start address of the corresponding TG. The corresponding */

   /* end address is inherently defined by the subsequent TG start address minus 1 (PENDx[TGx] =    */

   /* PSTARTx[TGx+1]-1). PSTARTx is copied into PCURRENTx when:*/

   for(i=0; i<8; i++){

      tgPSTART[i] = (mibspiREG1->TGCTRL[i] >> 8) & 0xFF;

   }

   /*MibSPI1 TG0, DMA config*/

   /* - creating a data chunk in system ram to start with ... */

   /* TXDATA_TG10 ->MibSPI1 TG0 */

   loadDataPattern(D_SIZE, &TXDATA[0], 0x5A00);

   dmaConfigCtrlTxPacket((uint32)TXDATA, (uint32)&(mibspiRAM1->tx[tgPSTART[0]].data), E_COUNT, F_COUNT);

   //using DAM_CH0 for RX, DMA_CH1 for TX

   /* - setting dma control packets */

   dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT_TX);  //tx

   dmaSetChEnable(DMA_CH1, DMA_HW);

   dmaReqAssign(DMA_CH1, DMA_REQ1); //DMA request line 1, TX

   // Set up the MIBSPI DMA channel triggers.

   uint32_t dmactrl_base1 = (1u << 31) /* ONESHOT */

                          | (1u << 14) /* TXDMAEN */

                          | (7u << 8) /* ICOUNT */;

   mibspiREG1->DMACTRL[0] = dmactrl_base1

                          | (7u << 24) /* BUFID */

                          | (0u << 16) /* TXDMA_MAP */;

#endif

   /* MibSPI3, Slave, TG0, DMA*/

   /* DMA source address: MibSPI RX RAM buffer 0 */

   /* DMA destination address: data array: RXDATA[] */

   /* DMA Channel 8, request line: 5*/

   dmaConfigCtrlRxPacket((uint32)&(mibspiRAM3->rx[0].data), (uint32)RXDATA, E_COUNT, F_COUNT);

   /* - setting dma control packets */

   dmaSetCtrlPacket(DMA_CH8,g_dmaCTRLPKT_RX);  //rx

   dmaSetChEnable(DMA_CH8, DMA_HW);

   dmaReqAssign(DMA_CH8, DMA_REQ5);

   /* Select the DMAxCOUNT counters. Writes to the DMAxCTRL register will not modify the ICOUNT value.

    * The ICOUNT value must be written to in the DMAxCOUNT register before the RXDMAENA or TXDMAENA bits are set in the

    * DMAxCTRL register. The DMAxCOUNT register should be used for reading COUNT or ICOUNT.

    * */

   mibspiREG3->DMACNTLEN = 0x1;

   mibspiREG3->DMACOUNT[0] = (F_COUNT*E_COUNT - 1) << 16;

   /* Set up the MIBSPI DMA channel triggers.

    * Oneshot is set. allows a block transfer of defined length (ICOUNTx+1)

    * BUFID is 0 (E_COUNT=1)

    * */

   uint32_t dmactrl_base3 = (1u << 31) /* ONESHOT */

                          | (1u << 15) /* RXDMAEN */

                          | (7u << 8) /* ICOUNT */;

   mibspiREG3->DMACTRL[0] = dmactrl_base3

                          | ((E_COUNT - 1) << 24) /* BUFID */

                          | (3u << 20) /* RXDMA_MAP */;

   /* Enable the DMA */

   dmaEnable();

   /* Enable MibSPI3 transfer group 0*/

   mibspiTransfer(mibspiREG3, 0);

   /* Write data directly to TX RAM buffers: 8 buffers are configured

    * The transmission delay between 2 buffers is defined in FMT0. It is 3.43us

    * */

   mibspiRAM1->tx[0].data = tx_data1[0];

   mibspiRAM1->tx[1].data = tx_data1[1];

   mibspiRAM1->tx[2].data = tx_data1[2];

   mibspiRAM1->tx[3].data = tx_data1[3];

   mibspiRAM1->tx[4].data = tx_data1[4];

   mibspiRAM1->tx[5].data = tx_data1[5];

   mibspiRAM1->tx[6].data = tx_data1[6];

   mibspiRAM1->tx[7].data = tx_data1[7];

   /* - start the mibspi transfer tg 0

    * Each transfer group has only 1 trigger event and trigger source. The trigger is issued when all the buffers in this

    * transfer group is ready to transfer

    *

    * This SW trigger is a pulse

    * */

   mibspiTransfer(mibspiREG1, 0);

while(1);

 /* USER CODE END */

   return 0;

}

/* USER CODE BEGIN (4) */

/** configuring mibspi dma with

*

*       channel   > mibspi dma channel number

*       txchannel > transmit channel dedicated for mibspi

*       rxchannel > receive  channel dedicated for mibspi

*/

void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)

{

   //uint32 bufid  = (channel + 1) * E_COUNT - 1;

   uint32 bufid  = tgPSTART[channel] + E_COUNT - 1;

   /* setting transmit and receive channels */

   mibspi->DMACTRL[channel] |= (rxchannel << 20) | (txchannel << 16);

   if (F_COUNT > 1) {

        mibspi->TGCTRL[channel] &= 0xBFFFFFFF; // Disable ONESHOT

   } else {

        mibspi->TGCTRL[channel] |= 0x40000000; // Enable ONESHOT

   }

   /* enabling transmit and receive dma */

   mibspi->DMACTRL[channel] |=  0x8000C000;

   /* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */

   mibspi->DMACTRL[channel] |=  (bufid<<24);

   /* Enable Large count transfer */

   mibspi->DMACNTLEN = 0x1;

   mibspi->DMACOUNT[channel] = (F_COUNT - 1) << 16;

}

void loadDataPattern(uint32 psize, uint16* pptr, uint16 pattern)

{

   int i;

   for(i=0;i<psize;i++)

   {

       *(pptr++) = pattern + i;

   }

}

void dmaConfigCtrlTxPacket(uint32 sadd, uint32 dadd, uint16 ElmntCnt, uint16 FrameCnt)

{

     g_dmaCTRLPKT_TX.SADD       = sadd;               /* source address             */

     g_dmaCTRLPKT_TX.DADD       = dadd;               /* destination  address       */

     g_dmaCTRLPKT_TX.CHCTRL     = 0;                  /* channel control            */

     g_dmaCTRLPKT_TX.FRCNT      = FrameCnt ;          /* frame count                */

     g_dmaCTRLPKT_TX.ELCNT      = ElmntCnt;           /* element count              */

     g_dmaCTRLPKT_TX.ELDOFFSET  = 4;                  /* element destination offset */

     g_dmaCTRLPKT_TX.ELSOFFSET  = 0;                  /* element source offset */

     g_dmaCTRLPKT_TX.FRDOFFSET  = 0;                  /* frame destination offset   */

     g_dmaCTRLPKT_TX.FRSOFFSET  = 0;                  /* frame destination offset   */

     g_dmaCTRLPKT_TX.PORTASGN   = PORTA_READ_PORTB_WRITE;                 /* port b                     */

     g_dmaCTRLPKT_TX.RDSIZE     = ACCESS_16_BIT;      /* read size                  */

     g_dmaCTRLPKT_TX.WRSIZE     = ACCESS_16_BIT;      /* write size                 */

     g_dmaCTRLPKT_TX.TTYPE      = FRAME_TRANSFER ;    /* transfer type              */

     g_dmaCTRLPKT_TX.ADDMODERD  = ADDR_INC1;          /* address mode read          */

     g_dmaCTRLPKT_TX.ADDMODEWR  = ADDR_OFFSET;        /* address mode write         */

     g_dmaCTRLPKT_TX.AUTOINIT   = AUTOINIT_OFF;       /* autoinit                   */

     //return g_dmaCTRLPKT_TX;

}

void dmaConfigCtrlRxPacket(uint32 sadd, uint32 dadd, uint16 ElmntCnt, uint16 FrameCnt)

{

     g_dmaCTRLPKT_RX.SADD       = sadd;              /* source address             */

     g_dmaCTRLPKT_RX.DADD       = dadd;           /* destination  address       */

     g_dmaCTRLPKT_RX.CHCTRL     = 0;                 /* channel control            */

     g_dmaCTRLPKT_RX.FRCNT      = FrameCnt;                 /* frame count                */

     g_dmaCTRLPKT_RX.ELCNT      = ElmntCnt;             /* element count              */

     g_dmaCTRLPKT_RX.ELDOFFSET  = 0;                 /* element destination offset */

     g_dmaCTRLPKT_RX.ELSOFFSET  = 4;                 /* element destination offset */

     g_dmaCTRLPKT_RX.FRDOFFSET  = 0;                  /* frame destination offset   */

     g_dmaCTRLPKT_RX.FRSOFFSET  = 0;                 /* frame destination offset   */

     g_dmaCTRLPKT_RX.PORTASGN   = PORTB_READ_PORTA_WRITE;   /* port b                     */

     g_dmaCTRLPKT_RX.RDSIZE     = ACCESS_16_BIT;      /* read size                  */

     g_dmaCTRLPKT_RX.WRSIZE     = ACCESS_16_BIT;      /* write size                 */

     g_dmaCTRLPKT_RX.TTYPE      = FRAME_TRANSFER ;   /* transfer type              */

     g_dmaCTRLPKT_RX.ADDMODERD  = ADDR_OFFSET;         /* address mode read          */

     g_dmaCTRLPKT_RX.ADDMODEWR  = ADDR_INC1;       /* address mode write         */

     g_dmaCTRLPKT_RX.AUTOINIT   = AUTOINIT_ON;       /* autoinit                   */

     //return g_dmaCTRLPKT_RX;

}