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TM4C123GH6PM: SSISR register and SSI Transmit/Receive FIFO

Part Number: TM4C123GH6PM

Hi,

Assuming I'm  sending 5 bytes and simultaneously I'll receive 5 bytes from the slave.

5 bytes are written to FIFO then SSI is enabled.

To know if the 5 bytes are transmitted, I would check if TFE is true.

Then I want to empty the received 5 bytes . I would check on while RNE is true keep reading the FIFO.

Is there any problem in checking the flags in the two case ?

Thanks

  • The TFE (transmit FIFO empty) flag becomes set when the fifth byte is transferred into the shift register. At that point you have only received four bytes. It is possible that if you read bytes polling on the RNE (receive not empty) flag, that you will read four bytes and stop polling before the fifth byte is received. You can check the BSY (busy) flag instead. It will not clear until all five bytes were transmitted and received. You could loop reading five bytes since you will always receive the same number of bytes as you send, although some may not contain meaningful information. Or you can use interrupts.
  • Thanks Bob that is a good answer as well as a good expression. However, what if the slave is dead or one of the 4-traces is broken . Is there a way to verify the solidity, integrity between the Master and slave instead of waiting forever ; for example when I enable the Master to start TX, I should check a flag to indicate the normality or abnormality of the condition between the Master and the Slave .
  • Even if there is not slave attached, the master will "receive" the same number of bytes as transmitted. The bytes may be all 0x00 or 0xFF (depending on the pullup/pulldown) but there will be that many bytes received. There is no self contained way to verify the master/slave connection. The best bet is to have a protocol established between master and slave where there is an expected response from the slave that the master can check.