TM4C1294KCPDT: MUX decodes have GPIO pin 0 (6) encodes are for APB not AHB

The datasheet leaves out a single word in the statement below perhaps leads to GPIO pin 0's being defined instead of the specific pin number specified in the call. The Tivaware DMUX values of (pin_map.h) are all set to GPIO pin 0 and should be the physical GPIO pin value set in REG22 of GPIOPCTL 0x524. There should be no shifting in the GPIOPCTL leading anyone to question (pin_map.h) defines below when debugging source by visual inspection methods. The MUX decode values of GPIO pins MUST be static table entries so quick inspection by visual checks can correlate a proper match to the visual port value in the call. Why anybody on earth would ever thrust shifting of GPIO pin mux values goes beyond any sound logic.

Far below is an example of GPIO decodes for PWM M0FaultN MUX configuration that visual inspection suggest GPIO pin 0 configured (6) matching datasheet 23.2, PWM module. The first thing anyone thinks is that can't be right then check out the GPIOConfigure() and scratch head wiggle a bit in their seat. Anyone who ever trusted GPIOPinConfigure() must explicitly go into CCS debug and verify ever single GPIOPCTL (pin_map.h) define actually shifted the GPIO pin number as seemingly the last step of call below preforms???? What if that last part in call screws up shifting bits of GPIO port MUX defines, then odd things start to happen don't they!

GPIOPinConfigure(uint32_t ui32PinConfig)
{
    uint32_t ui32Base, ui32Shift;

    //
    // Check the argument.
    //
    ASSERT(((ui32PinConfig >> 16) & 0xff) < 18);
    ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0);

    //
    // Extract the base address index from the input value.
    //
    ui32Base = (ui32PinConfig >> 16) & 0xff;

    //
    // Get the base address of the GPIO module, selecting either the APB or the
    // AHB aperture as appropriate.
    //
    if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ui32Base))
    {
        ui32Base = g_pui32GPIOBaseAddrs[(ui32Base << 1) + 1];
    }
    else
    {
        ui32Base = g_pui32GPIOBaseAddrs[ui32Base << 1];
    }

    //
    // Extract the shift from the input value.
    //
    ui32Shift = (ui32PinConfig >> 8) & 0xff;

    //
    // Write the requested pin muxing value for this GPIO pin.
    //
    HWREG(ui32Base + GPIO_O_PCTL) = ((HWREG(ui32Base + GPIO_O_PCTL) &
                                      ~(0xf << ui32Shift)) |
                                     ((ui32PinConfig & 0xf) << ui32Shift));
}

23.2 Signal Description:
The number in parentheses (6) is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 785) to assign the PWM signal to the specified GPIO port pin.

#define GPIO_PF4_M0FAULT0       0x00051006
#define GPIO_PK6_M0FAULT1       0x00091806
#define GPIO_PK7_M0FAULT2       0x00091C06