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TM4C123GH6PGE: Trying to sleep, waking up due to HIBERNATE_INT_WR_COMPLETE. EEPROMProgram question

Part Number: TM4C123GH6PGE


In progress porting a code base to new hardware.   The new hardware takes better advantage of the hibernate module and turns off the TM4C123 power supply.

What's happening is when the application goes to sleep, it wakes back up again.    It looks like the culprit is due to 'Write Complete' interrupt.   I have tried to mask that interrupt, but either not doing it the right way or something else is re-enabling.

if(ROM_HibernateIsActive())
{
  uiStatus = ROM_HibernateIntStatus(false);     // Read the status to determine cause of wake.
ROM_HibernateIntClear(uiStatus); // Clear the hibernate interrupt
... else if(uiStatus & HIBERNATE_INT_WR_COMPLETE) // 0x00000010 <<---- this bit is active { uprintf("\nWake by HIB INT WR COMPLETE"); sys_data.state = IDLE; // Drop through to main menu } ...

What I'm looking for is the proper way to handle EEPROMProgram.   See below for the EEPROMProgram statement, is there a way to poll for 'Write Complete'?   Can someone point me to an example.  Thanks

	// Let message print out
	UARTFlushTx(0);
	ROM_SysCtlDelay(MILLISECOND*250);
	console_off();

	// Save our sys_data variables before hibernating!
	// Copy the sys_data struct into EEPROM.  Last argument ensures # of bytes is multiple of 4
	if(EEPROMProgram((uint32_t*) &sys_data, 0x400, (sizeof(sys_data) + 3) & ~3))
	{
		uprintf("Error storing system data.\n");
		error_store("Error storing system data.");
		return;
	}


<<<----- What code should be placed here to wait for 'Write Complete'

	// Clear any pending interrupts
	ulStatus = ROM_HibernateIntStatus(0);
	ROM_HibernateIntClear(ulStatus);

	ROM_HibernateRTCTrimSet (0x7FFF);	// Make sure trim is set to default to prevent lockup (see errata)

	// Disable CPU control of GPIO pins (sets VDD3ON bit)
	HibernateGPIORetentionEnable();

	// Tell hibernation module we want to sleep
	ROM_HibernateRequest();

	ROM_SysCtlDelay(MILLISECOND);	// Give time to hibernate.

	// Shouldn't get to this point, something went wrong
	uprintf("\n\n\nHybernation error!\n\n\n");
	error_store("Hybernation error.");

  • The write complete signal has nothing to do with EEPROM. It is set when the hibernate module is ready to accept another write. This bit is read by the TivaWare routines that write to the hibernate module bits. It is not the masked write complete interrupt bit that is preventing the device from going into hibernate mode.

    Which wake source are you setting? If no wake-up source is configured, the device will not go into hibernate mode.

  • Thanks for the pointer, and wake sources are RTC and WAKE pin.

    Since the old hardware did not turn the regulator off and the new hardware does, it looks like the problem was due to VDD3ON bit.

    Since the new hardware has a power supply that is turned off during deep sleep, the VDD3ON bit should not be set. Removing the line that sets that bit then allowed deep sleep to occur. The WC interrupt looks like it was occurring as a result of incorrect setting of VDD3ON. I'm still reading the TRM (hardware users guide) to make sure I'm managing the hibernation module correctly.

    In the code I previously posted - removing the following line makes the sleep work.

    // Disable CPU control of GPIO pins (sets VDD3ON bit)
    HibernateGPIORetentionEnable();