When reading the data sheet/reference manual, it seems that A3 is a 'hard' N2HET1[29] and C3 is a "secondary terminal" where this signal is also available, presumably when configured. In our design, A3 is connected to input circuitry, the intention being it can be read and there would be logic level 0 or 1 (3.3V) on it. C3 is connected to output circuitry, and the intention is to be able to set this pin to a logic level 0 or 1 (3.3V). My question is how these pins are connected internal to the device. Could someone provide a diagram? If C3 is configured as an N2HET1[29] output, and A3 is configured to be read by input mux, can I configure C3 as a N2HET1[29] output pin and have it operate without interference with A3 (if I don't need to read A3 under certain conditions)?
I understand I could just configure C3 as a MIBSPI3NCS[3] gpio and avoid this entire issue, however there are compelling reasons why we need to keep it configured as N2HET1[29].
Note: we're using the N2HET1[29] purely as a gio under these conditions.
Thanks
