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EMIF Interface to 256K 16-bit SRAM

Tony Morrell
Genius 4130 points

Hi,

The Technical Reference Manual Figure 10-8 in section 10.3.1.1 describes the EMIF interface to an 8-bit RAM. Here A[18:0] and EMIFBADD[1:0] are used to form the SRAM 21-bit address A[20:0].

We wish to interface to a 16-bit SRAM (CY7C1041CV33) which allows 16-bit data access as well as high byte or low byte access from within the 16-bit word. To do this, you access the 16-bit word, and can then either select the 16-bit word (/BHE & /BLE low), the high byte (/BHE low, /BLE high) or low byte (/BHE high, /BLE low). I think we need to connect TMS570 [16:0] to SRAM A[17:1] and EMIFBADD[1] to SRAM A[0]. We then have the problem of byte select, driven by EMIFBADD[0]. Do I need to drive the SRAM byte select /BHE and /BLE from EMIFBADD[0]?

I see in the TMS570 datasheet that there are signals /EMIFDQM[1:0] described as 'EMIF Byte Enable pins'. Are these used to make the selection between low byte/high byte/both bytes? If so, they would correspond to my 16-bit SRAM signals /BHE and /BLE.

/EMIFDQM does appear in the TRM but is not described.

Any help would be much appreciated.

Regards, Tony.

  • 0
    TI__Mastermind 22375 points

    Tony,

    To connect an external 16bits memory with BLE/BHE for 8bits accesses, please follow this recommandation:

    EMIFADD[16:0] to SRAM_ADD[17:1]
    EMIFBADD1      to SRAM_ADD[0]
    EMIFDQM0        to SRAM_BLE
    EMIFDQM1        to SRAM_BHE

    The EMIF has to be programmed as following:

    Select Strobe = 0
    Enhanced Wait = 0
    Memory Size = 16
    SETUP Cycle Config = Slave Dependent
    HOLD Cycle Config   = Slave Dependent
    Strobe Cycle Config  = Slave Dependent

    In the TRM, the EMIF is described as 8 bits. This is not correct. The EMIF on TMS570LS series is 16bits data.

     

    Best Regards,

    Jean-Marc Mifsud

  • 0 in reply to Jean-Marc Mifsud
    Genius 4130 points

    Thanks again Jean-Marc for your speedy response.

    As a TI employee, I wonder if you have any influence on the content of the TRM (in this case). As I said, the signals EMIFDQM[1:0] are not actually described and an example 16-bit SRAM example would be useful in addition to that for the 8-bit SRAM.

    Regards, Tony.

  • 0 in reply to Tony Morrell
    TI__Mastermind 22375 points

    Tony,

    Normal 0 false false false MicrosoftInternetExplorer4

    In our process of continues improvement, we are taking in account all questions and comments on our forum.
    This specific EMIF question has already been send to the appropriate owner for specification enhancement/correction.

    I can’t guaranty when the TRM will be updated, but you can be sure that we will inform you when this update is available.

     

    Thanks and Regards,

  • 0 in reply to Jean-Marc Mifsud
    Genius 4130 points

    Hi Jean-Marc. That's good to know. I won't ask again. Thanks again for your help. Tony.

  • 0 in reply to Tony Morrell
    TI__Genius 13810 points

    This fix and the example (connecting to a 16bit SRAM) will be included in the next TRM release (TMS release in Nov).

    Thanks for advicing that,

    Haixiao