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TM4C1294KCPDT: PWM0 GEN1 A/B reversed in GPIO Pin Mux?

Guru 55913 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: TM4C1294NCPDT

Very strange issue  PWM pulses end up on GEN1 (A) high when they were directed to (B) low.

Hardware rings out to gate driver in correct orientation (custom PCB) and firmware is configured for GPIO pins that should not be crossing these signals.

Could it be the Pin Mux decode assignments are backwards for GEN1 in (pin_map.h) and the ROM / MAP directives makes no difference. This same firmware oddly was producing correct signals on GEN1 A/B on TM4C1294NCPDT even with GEN2 A/B revered in (pins.h) defines did not effect motor runs. That GEN2 cross was corrected on KCPDT recently but it was not expected GEN1 to be reversed too as it was GEN1 on TM4C1294NCPDT and had no issues on scope captures.

Below GEN1 configuration;

    // Enable PF2 pin 44 for Phase B High GEN1 M0PWM2
    ROM_GPIOPinConfigure(GPIO_PF2_M0PWM2);
    ROM_GPIOPinTypePWM(GPIO_PORTF_AHB_BASE, GPIO_PIN_2);
    //
    // Enable PF3 pin 45 for Phase B Low  GEN1 M0PWM3
    ROM_GPIOPinConfigure(GPIO_PF3_M0PWM3);
    ROM_GPIOPinTypePWM(GPIO_PORTF_AHB_BASE, GPIO_PIN_3);

  • Perhaps something more sinister is going on here. Switching High A for Low B produced nearly the very same signals on gate driver HO/LO outputs.
  • It is "proper" to note - that this appears to be the "least useful" (This Resolved) posting - ever?     Good that you've, "Cleared this up!"

  • Was and still are capturing many distorted pulses from GEN1 gate driver. Seems they are directly relative to dead band generator and PWM A/B equally delayed in gate driver matching logic.  

    Other words compatibility of software to work properly with a defective gate driver may be more an issue than ever believed possible on the surface.