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RTOS/TM4C1294KCPDT: How to enable single byte UART interrupt with FIFO

Peter Borenstein
Mastermind 8695 points
Part Number: TM4C1294KCPDT

Tool/software: TI-RTOS

Is there any way to receive a receive interrupt from a single received byte into a UART with the FIFO enabled?

The FIFOs are 16 bytes deep. The receive interrupt is triggered off ⅛, ¼, ½, ¾, and ⅞ full FIFO. The smallest value, 1/8 (UART_FIFO_RX1_8), would be 2 bytes.

My device receives an odd number of bytes in a UART packet. I would like an interrupt for a single byte without the needing to read the byte within one byte's transmit time.

  • 0
    TI__Guru 72500 points

    Use one of the FIFO interrupts and the "Receive Timeout" interrupt. That way, if a single character comes in with no character following within 32 (or 64) bit periods, you get an interrupt.

  • 0 in reply to Bob Crosby
    Mastermind 8695 points
    Bob, this is a clever workaround. My baud rate is 19,200, so this would give me a HWI after 1.7ms.

    For now, I think I will made due with no FIFO. Thank you for the advise.
  • 0 in reply to Peter Borenstein
    Guru 117855 points

    Disclaimer:  We've not implemented this - yet at the cost of, "One GPIO & One Split Timer" - a faster method (2x faster!) may be substituted.     (again - in "theory")

    This (unconfirmed) method follows:

    • Strap your signal to (both) "UART_RX" and to (ideally) a nearby (spare) GPIO.
    • Program that GPIO to, "Interrupt upon a "Falling Edge" - but only after (say) 2 UART Byte times have elapsed with the signal at "logic high."
    • Program the (added) split Timer to a value which will,  "Exceed one Byte Time" (i.e. one byte time's duration) + 10-20% (for safety)
    • At the expiration of this Timer - Read the GPIO.    If  the GPIO is "high" - it appears,  "Reasonable to assume that, "ONLY" a Single Byte" has arrived
    • At that (shortened) time - you may "read your UART's Single Byte."

    If this works - should this work - it is due to the:

    • Detection of the Negative Driving "Start Bit"
    • Followed by the "Timely Detection of the Stop Bit"
    • And sustained (10% beyond that Stop Bit) "Logic High"
    • And the likelihood that,  "Back to back" UART characters arrive w/minimal (or at least KNOWN/Predictable) "Inter-Character DELAY!" 

    The above suggests that (indeed) - (Only) a Single Byte has arrived.     And "alerts" w/in LESS THAN 16 UART BIT CLOCKS...     (again - may be "tweaked" to best accommodate,  "Inter-Character DELAY!")     Note that those (same) Inter-Character Delays will "equally impact" the (earlier/slower)  rmethod - yet may be "accounted for" - and  "overcome" - by this (unique & resourceful) method...

  • 0 in reply to cb1_mobile
    Mastermind 8695 points
    Good idea cb1. Such a PCB edit would cut the time until the interrupt by more than half.

    You proposed s similar idea for a poster seeking to detect bus activity in a half duplex system.
  • 0 in reply to Peter Borenstein
    Guru 117855 points
    Thank you Peter - appreciated.

    A "good/novel idea" - if it (truly) meets that spec. - should, "BE REUSED - ANY & EVERYWHERE" to maximize the, "Return on "Idea's Investment."

    Sometimes - knowing less about devices' "fine detail" - forces different methods of, "Problem Solving" which - on occasion - prove GREATLY VALUED by Clients...