CCS/RM57L843: Problem in initialization of mapClocks in RM57L843 MCU

Hello Jerome,

The correct sequence:
1. Configure PLL control registers with the largest value for the last-stage of the dividers (R-dividers)
2. Enable the Phased-Locked Loops (PLLs)
3. Trim the LPO
4. Wait for main PLL output to become valid.
5. Map the device clock domains to the desired clock sources
6. Reduce the values of the R-dividers in steps to attain the target PLL output frequency for both PLL1 and PLL2.

What is the crystal frequency? The maximum crystal frequency supported is 20MHz.

Hello Wang,
Thanks you very much for your fast reply.
The crystal frequency is 16 Mhz.
But the calculus of the frequencies was wrong because the RTI free running counter 0 was wrong.
These values are correct:

Oscillator frequency SSW_CAPTURE_COUNT (SSWPLL2) 15.3 Mhz
PLL Output frequency SSW_CLKOUT_COUNT (SSWPLL3) 293.3 Mhz

Why the RTI free running counter 0 is wrong?
Why the Trace Analyzer XDS560V2 stops to work when the program ends the clock configuration (Sys_PllCtl1: 0xFFFFFF70 = 0x20079500)?
The detailed sequence is the following:

Disable the PLL : Sys_CsDisSet = 0x00000042
Wait for PLL Disabled : Sys_CsDis = 0x00000042
Clear Global Status Register : Sys_GlbStat = 0x00000301
Configure PLL control registers : Sys_PllCtl1 = 0x3F079500
Setup pll control register 2, Setup spreading rate, Setup bandwidth adjustment, Setup internal Pll output divider, Setup spreading amount : Sys_PllCtl2 = 0x3FC0703D
Setup pll2 control register, setup Pll output clock divider to max before Lock,Setup reference clock divider,Setup internal Pll output divider, Setup Pll multiplier : Sys2_PLLCTL3 = 0x1F079500
Enable PLL(s) to start up or cLock : Sys_CsDisClr = 0x00000042
Load TRIM values from OTP : Sys_LpoMonCtl = 0x0100120D
Wait for PLL Enabled : Sys_CsDis and 0x00000042 = 0
Setup system clock divider for HCLK : Sys2_HCLK1Ctrl = 0x00000001
Disable clock domain 0xFFFFFF3C (Sys_CdDis) = 0x00000020
Wait for the clocks domain are locked
Sys_GhvSrc = 0x01010001. Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup [0xFFFFFF74] = 0x3FC0703D
Setup RTICLK1 and RTICLK2 clocks : Sys_RclkSrc = 0x01090109
Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 : Sys_VlckASrc = 0x00000909
Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 : Sys_ClkCntl = 0x01010100
Sys_ClkCntl = 0x01010100
Sys2_CLK2CNTRL = 0x00000101
Sys2_VCLKACON1 == 0x00090009
The R-divider (programmed to 0xF). is changed to new value : Sys_PllCtl1 = 0x20079500 (The XDS560V2  trace analyzer stops to work at this point)
(Sys2_PLLCTL3) = 0x00079500
0xFFFFFF74 (Sys_PllCtl2) = 0x3FC0703D

Thanks for your help.

Jerome