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TMS570LS0714: Source of InitDbg bit #16 of the CAN control register

FJ Kime
Prodigy 110 points
Part Number: TMS570LS0714

When enabling interrupts for DCAN can_reg_n->ctl = (uint32_t)(MCAL_CTL_ABO | MCAL_CTL_PMD | MCAL_CTL_IE0 | MACL_CTL_IE1 | MCAL_CTL_SIE | MCAL_CTL_EIE), bit #16 of the CTL register (test mode per Table 24-7 of the TRM) is also set indicating "Debug mode requested and internally entered; the DCAN is ready for debug accesses".


What are the sources of this mode besides for bit #7 of CTL (test mode enable bit of offset 0x00) which I have set to zero?

Does this bit affect operation of the DCAN if set?

  • 0
    TI__Guru**** 196856 points
    Hello Kime,

    The Debug/Suspend mode should not be enabled for normal CAN operation. If this mode is enabled, the Message RAM cannot be accessed via the IFx register sets. But the Message RAM content is accessible via VBUSP interface.

    For all test modes (internal loopback, silent, external loopback, etc), the Test bit in the CAN Control Register needs to be set to 1. This enables write access to the Test Register. The test mode is selected from Test Register.

    Test mode is different from the Debug/Suspend mode.

    can_reg_n->ctl = (uint32_t)(MCAL_CTL_ABO | MCAL_CTL_PMD | MCAL_CTL_IE0 | MACL_CTL_IE1 | MCAL_CTL_SIE | MCAL_CTL_EIE);

    From this line, I don't see the variable for #16 bit