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TMS570LS3137: EMAC module is initialized but no packets are sent

hany elshahawy80
Prodigy 100 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN, TMS570LC4357

Hi all,

I am using IAR compiler to implement ethernet driver. I have been playing around with halcogen generated code and code composer studio and i can see the packets being sent on wireshark. 

So i initialized emac, mdio and emac control modules as shown in data sheet and as done in halcogen generated code. i create single buffer descriptors with proper flags and data array then add the address to TX0HDP register. I can see the TXGOODFRAMES number is incrementing but i still can not read the ethernet packets on wireshark.

Am i missing something extra to do?

Thanks,

Hany

  • 0
    TI__Guru**** 199106 points
    Hi Hany,

    Both projects (CCS and IAR) use the same drivers generated through HALCoGen. The CCS project works fine, but the IAR project doesn't transfer the packet correctly. Is my understanding correct?

    Did you try the loopback code to make sure the emac/phy is configured correctly?
  • 0 in reply to QJ Wang
    TI__Guru**** 199106 points

    #include "sys_common.h"
    #include "system.h"

    /* USER CODE BEGIN (1) */
    #include "emac.h"
    #include "hw_reg_access.h"
    /* USER CODE END */

    /** @fn void main(void)
    * @brief Application main function
    * @note This function is empty by default.
    *
    * This function is called after startup.
    * The user can use this function to implement the application.
    */

    uint8 emacAddress[6U] = {0x00U, 0x08U, 0xEEU, 0x03U, 0xA6U, 0x6CU};
    uint32 emacPhyAddress = 1U;

    /* USER CODE BEGIN (2) */
    extern hdkif_t hdkif_data[1];
    pbuf_t pack[5];
    static uint8 data[5][100];
    uint32 size1 = 470,size2=94;

    void create_packet()
    {
    int i,j;

    for(i=0;i<5;i++)
    {
    pack[i].tot_len = size1;
    pack[i].len = size2;
    for(j=0;j<6;j++)
    {
    data[i][j] = 0xffu;

    }
    for(j=0;j<6;j++)
    {
    data[i][j+6]= emacAddress[j];

    }

    data[i][12] = 0;
    data[i][13] = 80;

    for(j=0;j<80;j++)
    {
    data[i][j+14] = i+5;
    }

    pack[i].payload = &data[i][0];
    if(i!=4)
    pack[i].next = &pack[i+1];
    }
    pack[4].next= NULL;
    }
    /* USER CODE END */

    void main(void)
    {
    /* USER CODE BEGIN (3) */
    _enable_IRQ();
    EMACHWInit(emacAddress);
    create_packet();
    EMACTransmit(&hdkif_data[0], &pack[0]);
    size1=600;
    size2=120;
    create_packet();
    EMACTransmit(&hdkif_data[0], &pack[0]);

    while(1);
    /* USER CODE END */
    }

  • 0 in reply to QJ Wang
    Prodigy 100 points

    Hello QJ,

    Exactly, so i try this code with code composer studio and everything is working fine and i can see the packets. I try writing my own code and sending same packets on IAR compiler but i get nothing on ethernet cable and registers show me that all of TX frames are good frames as per manual. I will try to enable loopback but i do not know how can i know if something is wrong??
    Thanks  

  • 0 in reply to hany elshahawy80
    TI__Guru**** 199106 points
    Hello Hany,

    I am sorry I don't have license of IAR workbench, so I could not test it. Is it related to the memory map and section map defined in the linker.cmd file if using CCS.
  • 0 in reply to QJ Wang
    Prodigy 100 points

    Hello QJ,

    I just have a question, what does the incrementing of TXGOODFRAMES mean exactly? does it mean the frames are sent from the chip to phy successfully? or it means that the frames are sent from phy on the cable? I am struggling to know where the bug is but still no luck. 

    One other thing, when are the frames transmitted to CPPI ram? should this be the last step before being sent??

    Regards,

    Hany

  • 0 in reply to hany elshahawy80
    Prodigy 100 points
    I think for some reason the data is not written in the CPPI ram after i update the TXnHDP register with the pointer to the buffer descriptor. Is there something i am missing to make the DMA working?
  • 0 in reply to hany elshahawy80
    TI__Guru**** 199106 points
    Do you see the interrupt flag in TXPEND field of MACINVECTOR register?

    When the EMAC completes the transmission of a packet, the EMAC issues an interrupt to the CPU (via the EMAC control module) when it writes the packet’s last buffer descriptor address to the appropriate channel queue’s transmit
    completion pointer located in the state RAM block.
  • 0 in reply to QJ Wang
    Prodigy 100 points

    No it is not being set. 

  • 0 in reply to hany elshahawy80
    Prodigy 100 points
    I figured out that i get "Zero buffer length" error from MACSTATUS register. I initialize the empty linked list to be in CPPI ram and then populate it with data before writing the address to TXnHDP register. Does this sound correct?
    Regards,
    Hany
  • 0 in reply to hany elshahawy80
    Prodigy 100 points
    Sorry one more thing, the idle bit in MACSTATUS register is not deasserted. I saw in CCS that it is deasserted and emac is not in idle state upon enabling broad cast.
  • 0 in reply to hany elshahawy80
    TI__Guru**** 199106 points

    Hi Handy,

    TMS570LC4357 is a big endian device, so the descriptor written to TXnHDP should be swizzled. The CCS project has the if-else to swizzle the data based on the device name.

    If IAR doesn't have __rev() function, please use the following function to replace (this is my code for your reference): 

    int swizzledata(int indata)
    {
      #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
        return(indata);
      #else //big endian
        int outdata=0;
        outdata =((indata&0xFF)<<24)|((indata&0xFF00)<<8)|((indata&0xFF0000)>>8)|((indata&0xFF000000)>>24);
        return(outdata);

      #endif
    }

  • 0 in reply to QJ Wang
    Prodigy 100 points

    Hello QJ,

    I think the device is configured properly regarding endiannes. I can see that idle bit in MACSTATUS register is what causing the problem. i copied same initialization steps for EMAC,MDIO and IOMM i did in IAR to CCS and everything is working fine. it looks like i am missing something else, may be regarding the clock of emac module?? i have seen it is using vclk3 which i am enabling already. Is there a way to test if it is running normally?

    Hany

  • 0 in reply to hany elshahawy80
    TI__Guru**** 199106 points
    Hany,

    I think the clock settings should be fine since it works in CCS. The reading and writing from/to the registers doesn't using swizzle function. Please double check the CPPI RAM to make sure the packet data is in correct endianess format.
  • 0 in reply to QJ Wang
    Prodigy 100 points

    Hello QJ,

    I have checked the cppi ram and endiannes is fine. I think the main issue is that when running on CCS the idle bit is cleared indicating that EMAC is not idle. On IAR the idle bit stays 1 and never cleared. Does idle state of EMAC mean that it is not working? I can not find related information in data sheet,

    regards

  • 0 in reply to hany elshahawy80
    Prodigy 100 points
    Hello QJ,

    So after lots of debugging i found where the problem is. In CCS i can see that both registers PINMMR25[0:7] and PINMMR29[24:31] are set to zeros which i did not do because it is not mentioned in the emac module section in data sheet. I set it to zeros and finally i am getting packets.
    Thanks for your help,
    Hany