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RM57L843: The RM57L843 Machine instructions require more cycles to be executed

Part Number: RM57L843
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am trying to initialize an application on RM57L843 without HALCoGen, in assembly language.
After the initialization in assembly language the application run more slowly than after the initialization with HCG HALCoGen.

The clocks seems to be good and when I trace a loop test I can see that the same instructions require more cycles to be executed after the initialization in assembly language.

With HCG the loop require 32 cycles:

Disassembly:string                         Cycl        D.Cycl

ldr       r1, [r10, #0x10]                      0             2

sub       r1, r1, r0                               2             1

add       r3, r3, #1                              3             1

cmp       r2, r1                                   4              0

bpl       #0x7d74                                4             28

ldr       r1, [r10, #0x10]                      32           2

 

With the initialization in assembly language loop requires more than 60 cycles:

Disassembly:string                         Cycl        D.Cycl

ldr       r1, [r10, #0x10]                      0             5

sub       r1, r1, r0                               5             1

add      r4, r4, #1                               6             1

cmp       r2, r1                                   7             0

bpl       #0x1800cc                            7             53

ldr       r1, [r10, #0x10]                     60           5

 

What can be the cause of these differences?
Thanks for your help.

Jerome

  • Hello Jerome,

    1. check the number of the address and data wait states for the main flash:
    FRDCNTL register
    2. or copy the instructions to SRAM and execute those instructions in SRAM: doesn't have wait states for SRAM
    3. Configure ECLK to monitor the VCLK clock (VCLK/x) to make sure the HCLK, VCLK are set correctly.
  • Hello Wang,

    Thanks very much for your fast reply.

    The FRDCNTL register = 0x00000303 so there are 3 wait states. But this value is the same with the HALCoGen configuration and there is no problem with HALCoGen.

    I tried to execute the test loop in RAM but I got a prefetchEntry Exception with HALCoGen and assembly initialization.

    The HCLK and VCLK are set identically with HALCoGen and the assembly initialization.

    Best regards

    Jerome

     

     

     

  • Hello Wang,
    I have found the source of the issue.
    The instructions cache was not enabled: bit I and C (12 and 2) of the SCTLR register.
    Now all is working well.
    Thanks for your cooperation.
    Jerome