TM4C123GH6PM: Timer in RTC Mode

Hi Asif,

 Sorry, I misunderstood you.

 In this case, you will supply the 32kHz clock input to the CCP0.

11.3.2.2 Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as an up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM
Timer n Interval Load (GPTMTnILR) registers (see page 756). If the GPTMTnILR register is loaded
with a new value, the counter begins counting at that value and rolls over at the fixed value of
0xFFFFFFFF. Table 11-7 on page 711 shows the values that are loaded into the timer registers when
the timer is enabled.
Table 11-7. Counter Values When the Timer is Enabled in RTC Mode
Register Count Down Mode Count Up Mode
GPTMTnR Not available 0x1
GPTMTnV Not available 0x1
GPTMTnPS Not available Not available
GPTMTnPV Not available Not available
The input clock on a CCP0 input is required to be 32.768 KHz in RTC mode. The clock signal is
then divided down to a 1-Hz rate and is passed along to the input of the counter.

Hi Asif,

 Is your problem resolved?

 Not entirely sure what are you trying to do with the Timer in RTC mode. Based on your code, you are not configuring the RTC mode correctly. Please also refer to the datasheet for the Timer in RTC mode operation. Basically, the timer in RTC mode will start with a value of 1 after RTC mode is enabled. When you load the Timer Interval Load register with the value of 5,  you will then preset the counter to 5 and it will continue to count starting from 5 until it roll over at 0xFFFFFFFF. Since you have your match value set to 3 then it will never match until the the timer roll over the 2nd time until it reaches 3 which will take a very long time. 

Please see below excerpt on the RTC mode operation from the datasheet.

11.3.2.2 Real-Time Clock Timer Mode

Real-Time Clock Timer Mode

In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers

are configured as an up-counter. When RTC mode is selected for the first time after reset, the

counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM

Timer n Interval Load (GPTMTnILR) registers (see page 756). If the GPTMTnILR register is loaded

with a new value, the counter begins counting at that value and rolls over at the fixed value of

0xFFFFFFFF. Table 11-7 on page 711 shows the values that are loaded into the timer registers when

the timer is enabled.

The input clock on a CCP0 input is required to be 32.768 KHz in RTC mode. The clock signal is

then divided down to a 1-Hz rate and is passed along to the input of the counter.

When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from

its preloaded value of 0x1. When the current count value matches the preloaded value in the

GPTMTnMATCHR registers, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting

until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer

value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the

RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and

generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.