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TMS570LC4357: HET/PWM Generator question

Sunni Utt
Prodigy 145 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Questions related to the PWM output using the N2HET timer module for TMS570 processor:

 

1)     What is the frequency range that the PWM output can be generated?

2)     How many PWMs output can be generated at any particular time?

3)     Are there sample / driver codes that are available for this?

  • 0
    TI__Guru**** 199006 points
    Hello Sunnit,

    1. Normally the 75mHz of VCLK is used (maximum is 110MHz), NHET HR (high resolution) clock can be as fast as VCLK (75mHz). If the loop resolution clock (LR) is HR/32 (configurable), if the ECMP is used to generate PWM. The counter value is PWM period/loop resolution clock period-1
    This means that the maximum PWM frequency can be LR/(counter value+1). If Maximum counter CNT_max=1, the PWM freq is vclk/(32*2)=75/64 mhz
    2. You can use all the NHET pins to output PWM waveform
    3. HALCoGen can be used to configure the NHET pin for PWM, capture, and edge detection, and generate the code. HET IDE can be used to do simulation.
  • 0 in reply to QJ Wang
    Prodigy 40 points

    thx QJ,  followup questions:

    1) Concurrent operation: with the HET port, does it allow me to use half of the pins for input (counters) and the other half as output (PWM) with degradation to performance?

    2) I assume I can update the PWM output setting on individual output signals without impacting the operation of the other signals?

    3) can the PWM settings be updated realtime? or does it require re-initialization of the processor each time the PWM settings need to be changed?

    4) when I update the PWM output setting (e.g. change the duty cycle from 10% to 50%), how long does it take for the effect to take place from the moment the microcode is inserted? 

    5) Also, how does it impact the output of the signal during the setting transition?  For instance, if I change the output of the PWM from 400 HZ to 3000 Hz,  would there be a brief period where the signal is null? how long would that be?

    Thanks,

    C

  • 0 in reply to C.
    TI__Guru**** 199006 points
    Hello,

    1) If you want to use high resolution feature for PWM and counter (edge counter, or period measurement). "HR Structures Sharing" is used for counters, and "AND / XOR-shared HR Structure" is used for PWM.

    "HR Structures Sharing":
    The HR Share Control Register (HETHRSH) allows two HR structures to share the same pin for input capture only. If these bits are set, the HR structures N and N+1 are connected to pin N. In this structure, pin N+1 remains available for general purpose input/output. Two NHET pins are used for 1 counter (edge detection, etc), but the odd (n+1) pin can be used as GPIO.

    "AND / XOR-shared HR Structure"
    The HETXOR register allows a logical XOR of the output signals of two consecutive HR structures N (even) and N+1 (odd). In this way, it is possible to generate pulses smaller than the loop resolution clock since both edges can be generated by two independent HR structures. This
    is especially required for symmetrical PWM. Two pins are used for one PWM. The odd pin (n+1) can be used for GPIO.

    2) Yes, you can update the setting on individual output signals without impacting the operation of the other signals

    3) Yes. MOV32 and MOV64 are used to update the parameters (duty cycle, and period) for PWM.

    4) It takes effect in next LRP (LR clock). For example, if the VCLK=80MHz and NHET HR clock =80MHz, LR clock=80/128=625KHz, for 1KHz PWM output, one PWM period is 625 LR clocks.

    5) No, there is no null period.