TMS570LC4357: Errata CORTEX-R5#7 (ARM ID-780125) question regarding usage of write-back memory with cache-ECC

rp3

Part Number: TMS570LC4357

Hi,

The errata CORTEX-R5#7 (ARM ID-780125) suggests a work-around to avoid deadlock or data loss when using cache-ECC: setting the ACTLR.DBWR bit to 1.

It is unclear to me if additionnally to this work-around, the write-back attribute should or should not be used for the different memory regions of the TMS.

It is written that "This setting also disables generation of AXI bursts by the processor for Write-Through and Non-cacheable Normal memory, but not Write-Back memory."

So can I use the write-back attribute for SRAM, external memories, etc. ? or am I forced to use write-through attribute (which reduces significantly the performance of the cache) ?

Thank you in advance for your answer.

Best regards,

over 7 years ago

0 QJ Wang over 7 years ago

TI__Guru**** 197826 points

Hello RP,

My understanding is that setting DBWR bit will disable write burst to the memory (cacheable or non-cacheable, write-through or write-back). I will check with the designer.

0 rp3 over 7 years ago in reply to QJ Wang

Prodigy 120 points

Thank you QJ, I'm looking forward to hearing from you on this subject.

It is confusing for me that the issue starts with "When Write-back cache is selected..." (so this mode seems to be the issue) and that the workaround paragraph explains the DBWR does not disable the AXI bursts for Write-back.

I really need to be sure if I can or cannot use the Write-back mode at all when the workaround is applied...

Best regards

0 QJ Wang over 7 years ago in reply to rp3

TI__Guru**** 197826 points

Hello RP,

I talked with design guy. This erratum is from ARM, and we need to check with ARM design team.

0 rp3 over 7 years ago in reply to QJ Wang

Prodigy 120 points

Thank you QJ, I really appreciate it.

Regards,

0 rp3 over 7 years ago in reply to rp3

Prodigy 120 points

Hello QJ,

Any news from ARM on this topic ?

Thank you and regards,

0 rp3 over 7 years ago in reply to QJ Wang

Prodigy 120 points

Hello QJ

Still no news from ARM ?

Thanks and regards,

0 QJ Wang over 7 years ago in reply to rp3

TI__Guru**** 197826 points

Hello RP,

I am sorry I haven't got feedback. I will re-send an email again to address this issue: ARM ID-780125. Thank you for your patience.

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TMS570LC4357: Errata CORTEX-R5#7 (ARM ID-780125) question regarding usage of write-back memory with cache-ECC