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TM4C1294NCPDT: PWM Generator’s time base synchronisation in up-down count mode with different load or period-match values.

Part Number: TM4C1294NCPDT

I am using PWM generator-0 and generator-1 (total 4PWMs) to generate center-aligned PWM @ 20kHz for single-phase H-bridge circuit.

I want to run control-loop ISR at half of PWM frequency at 10kHz as well trigger ADC for current sense at 10kHZ using PWM generator-2 as shown in figure below. Is it possible to synchronise PWM-Generator-2 time base with double of load value with PWM generator0 and 1 in up-down mode?

  • Hello Milan,

    It doesn't look like your image uploaded to E2E properly, can you please try adding it again?
  • Hello Ralph,

    Please check above image.

  • Hello Milan,

    Thank you for the image, very helpful for my understanding which is quite crystal clear now.

    The answer unfortunately is the fabled: "It Depends"

    How tight do you need the synchronization to be?

    How often would you be willing to re-synchronize the signals?

    Those two questions will be very key in determining what is possible.

    In general, the best that can be done for synchronization with two different periods is to clear their counters as closely together as possible. Using the Sync API's do this quite well, but the synchronization doesn't last forever and actually initial degrades quite quickly as within 3-4ms, there is already 300-400ns error in the synchronization. The longer it is left without re-syncing, the more it will get out of sync, at a rate that seems to be roughly 25ns per ms (from just a few crude measurements and calculations).

    If you have no tolerance for even small variation or cannot resync often, then based on my findings you wouldn't be able to do what you are hoping for.

    Here is the code I used to try this out. I realize now posting this that you also needed center aligned which this doesn't reflect, but I think the principle will be the same.

        uint32_t ui32SysClock;
    
        ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 120000000);
    
        SysCtlPWMClockSet(SYSCTL_PWMDIV_1);
    
        SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM0);
    
        SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
        SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    
        GPIOPinConfigure(GPIO_PK4_M0PWM6);
        GPIOPinConfigure(GPIO_PG1_M0PWM5);
    
        GPIOPinTypePWM(GPIO_PORTK_BASE, GPIO_PIN_4);
        GPIOPinTypePWM(GPIO_PORTG_BASE, GPIO_PIN_1);
    
        PWMGenConfigure(PWM0_BASE, PWM_GEN_3, PWM_GEN_MODE_DOWN | PWM_GEN_MODE_GEN_SYNC_LOCAL);
        PWMGenConfigure(PWM0_BASE, PWM_GEN_2, PWM_GEN_MODE_DOWN | PWM_GEN_MODE_GEN_SYNC_LOCAL);
    
        PWMGenPeriodSet(PWM0_BASE, PWM_GEN_3, (ui32SysClock / 10000) - 1);
        PWMPulseWidthSet(PWM0_BASE, PWM_OUT_6, (ui32SysClock / 50000) - 1);
    
        PWMGenPeriodSet(PWM0_BASE, PWM_GEN_2, (ui32SysClock / 20000) - 1);
        PWMPulseWidthSet(PWM0_BASE, PWM_OUT_5, (ui32SysClock / 50000) - 1);
    
        PWMOutputState(PWM0_BASE, PWM_OUT_6_BIT | PWM_OUT_5_BIT, true);
    
        PWMGenEnable(PWM0_BASE, PWM_GEN_3);
        PWMGenEnable(PWM0_BASE, PWM_GEN_2);
    
        PWMSyncTimeBase(PWM0_BASE, PWM_GEN_2_BIT | PWM_GEN_3_BIT);
        PWMSyncUpdate(PWM0_BASE, PWM_GEN_2_BIT | PWM_GEN_3_BIT);
    
        while(1)
        {
        	// Do Nothing
        	SysCtlDelay(500000);
            PWMSyncTimeBase(PWM0_BASE, PWM_GEN_2_BIT | PWM_GEN_3_BIT);
            PWMSyncUpdate(PWM0_BASE, PWM_GEN_2_BIT | PWM_GEN_3_BIT);
        }

  • Hi Milan,

    Also thinking along the lines of your application needs specifically, I wonder if a Timer would be better served if you were able to keep it similarly in sync with the PWM. Again, how tightly the synchronization needs to be would determine the viability, but I think there could be some good advantages to the timer being used as you could trigger the ADC from the timer. Also what would the zero count ISR be used for? That is unclear.
  • Hello Ralph,

    Thanks for detail explanation, though it seems I can not use TIVA exactly my application needs.

    I need PWM timers to be in sync always as current sensing in H-bridge is critical to be aligned with period matches otherwise it leads to error in sensing due to 20kHz switching ripple. Zero current ISR will be used for closed control loop software execution for voltage/current PI controllers and duty cycle calculation etc.

    I figured out another way to go around it with little overhead in software. I will trigger ADC and ISR at 20KHz itself but use alternate cycles for ADC values and execute control ISR.

    Best Regards
    Milan
  • Hi Milan,

    You are aware the TM4C1294 PWM0 can not do true ZVSFB, zero voltage phase shifted H bridge commutation? It can switch two inductive legs at zero volts from two overlapping generators A/B signals with zero flag synchronous updates occurring. Seemingly the phase shift is inherited by design from A/B uneven duty cycles in the period. Other words you can not easily set the amount of desired phase shift between any two synchronous generators without the use of a GPTM in the mix.

    That said if you do not need to adjust the power level via the resulting overlapping phase shift then it may work ok. Otherwise the Piccolo F280x is a better choice MCU for ZVSFB with a phase control register to make easy adjustments.
  • Hello BP101,

    Thanks for your inputs, though my need is not Phase shift modulation, rather two interleaved buck converters, Gen-0's two PWMs for one pair of interleave buck and Gen-1 PWMs for other pair of buck converters. I am able to generate interleaved PWMs quite successfully using TIVA only thing I need is to execute control loop ISR and ADC triggering at half of switching frequency rate therefore I wanted to synchronise Gen-2 at 1/2 half of Gen-0/1's frequency.

    I agree with your point that Piccolo is right choice for such power application.

    Best Regards
    Milan
  • milan rajne said:
    only thing I need is to execute control loop ISR and ADC triggering at half of switching frequency rate therefore I wanted to synchronise Gen-2 at 1/2 half of Gen-0/1's frequency

    PWM0 module should be able to update waveform during each zero flag (GEN0) and maintain half interleaved frequency (GEN1) via waveform updates as Ralf mentions drifting otherwise occurs.