TM4C129XNCZAD: PLL freq is half what I expect

Dave Hohl

Part Number: TM4C129XNCZAD

I am using the TM4C129X dev kit, which uses a 25 MHz crystal oscillator. The TivaWare version I am using is 2.1.4.178. I have the following code to initialize the system clock:

    systemClockFreqHz = SysCtlClockFreqSet( (       SYSCTL_XTAL_25MHZ
                                                |   SYSCTL_OSC_MAIN
                                                |   SYSCTL_USE_PLL
                                                |   SYSCTL_CFG_VCO_480
                                            ), 120000000U);

When I call SysCtlVCOGet() to check the PLL frequency, it returns 240000000 rather than the 480000000 I expect. If I look at the PLL registers, MINT=0x60, MFRAC=0, N=4 and Q = 1. According to table 5-7 in the chip data sheet, I should be getting a PLL of 480000000 if Q were equal to 0. But for some reason the SysCtlClockFreqSet() function has set Q to 1. How can I get a PLL of 480000000 ?

Regards,

Dave

over 7 years ago

0 Dave Hohl over 7 years ago

Expert 2315 points

The code I used to set the system clocked worked fine on a previous project, which used an earlier version of TivaWare. I did a diff between the sysctl.c files in the previous and current versions of TivaWare, and found a curious change:

OLD:

//*****************************************************************************
//
// Look up of the possible VCO frequencies.
//
//*****************************************************************************
static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] =
{
320000000, // VCO 320
480000000, // VCO 480
};

NEW:

The g_pppui32XTALtoVCO[ ] table also seems to have been updated to add a Q value, and it looks like the table is setting Q to 1 for the 25 MHz case:

//
// VCO 480 MHz
//
{ PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz
{ PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz
{ PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6 MHz
{ PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz
{ PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz
{ PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz
{ PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz
{ PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz
{ PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12 MHz
{ PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz
{ PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz
{ PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz
{ PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz
{ PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz
{ PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 18 MHz
{ PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz
{ PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 24 MHz
{ PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz

Could it be that something got messed up in the latest TivaWare version?

Regards,

Dave

0 Bob Crosby over 7 years ago in reply to Dave Hohl

TI__Guru 72500 points

The change is intentional. It is part of the workaround for erratum SYS#22.

0 Dave Hohl over 7 years ago in reply to Bob Crosby

Expert 2315 points

So does that mean it is not possible to set a PLL freq of 480000000 then?

Regards,

Dave

0 Bob Crosby over 7 years ago in reply to Dave Hohl

TI__Guru 72500 points

There are issues with running the VCO at 480MHz that the latest TivaWare avoids by running it at 240MHz to generate the 120MHz system clock. May I ask why you desire to run the VCO at 480MHz? Perhaps I might be able to suggest a different solution.

0 Dave Hohl over 7 years ago in reply to Bob Crosby

Expert 2315 points

Hi, Bob,

The reason I wanted to run the PLL at 480 was because I originally thought it needed to be that for the USB to run at max speed. But after reading the data sheet a bit more carefully it looks like the PLL gets divided down to create a 60 MHz clock, so it doesn't really matter if the PLL is 480. Am I understanding that correctly?

Regards,

Dave

0 Bob Crosby over 7 years ago in reply to Dave Hohl

TI__Guru 72500 points

Yes, that is correct.

0 Dave Hohl over 7 years ago in reply to Bob Crosby

Expert 2315 points

OK, thanks Bob. I guess it is not really a problem then.

Regards,

Dave

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TM4C129XNCZAD: PLL freq is half what I expect