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How to use HET to generate PWM signal



Hi,

  I've successfully assembled HET file and compiled my project files without any error.

 However, pin HET0 and HET1 are not toggling as they should be, not as coded in HET.

The flow of the code:

     Basically, in main( ), there is a forever loop to blink LEDS using port GIOA[7:0], and generate PWM output on pin HET0 and HET1. The LEDS are blinking just fine (the on-and-off duration can be controlled through SYSCLK setting, ICLK setting and delay loop), but both the HET0 and HET1 pins have no activity.

 

The following are my main.c and HET_pwm files.

Any ideas what setting that I've missed in my main() or in HET_pwm.het? What have I done wrong?

Any help is appreciated. Thank you!

-----------------------------------------------------------------------------------------------------------------------------------------------------

Note: Clock setup -> SYSCLK = Foscin = 14.7456Mhz, peripherals clock, ICLK = SYSCLK, and HET clock = SYSCLK

Software Tool: IAR Embedded Workbench

main.c

#include <stdio.h>
#include <string.h>
#include <intrinsic.h>
#include "std_het.h"
#include "tms470.h"
#include "HET_pwm.h"

#ifdef R1VF689
#include "iotms470r1vf689.h"
#else
#include "iotms470r1vf348.h"
#endif

__no_init volatile HETPROGRAM0_UN e_HETPROGRAM0_UN @ 0x00800000;


//------------------------------------------------------------------------------
// Help function to load the HET program into the HET RAM using 32-bit access.
//------------------------------------------------------------------------------
void MemCopy32(unsigned long *dst, unsigned long *src, int bytes)
{
  for (int i = 0; i < (bytes + 3) / 4; i++)
    *dst++ = *src++;
}



int main()
{
     // Init SYSCLK, Foscin = 14.7456Mhz
    GCR = 0x00000007; // set SYSCLK = (Foscin * 8)/8
    // Enable peripherals and set clock to SYSCLK
    PCR = 0x00; // set ICLK = SYSCLK
    PCR |= 0x1; // enable peripherals
    // Set pin CLKOUT
    CLKCNTL_bit.CLKSR = 0x3;// set pin CLKOUT = SYSCLK
   
        __enable_interrupt(); // Enable interrupts.

    // Init GIOA as output
    GIODIRA = 0xFF;
    // Set the output low
    GIODOUTA = 0x00;
   
        // Copy HET instructions to HET RAM
        MemCopy32((void *) &e_HETPROGRAM0_UN, (void *) HET_INIT0_PST, sizeof(HET_INIT0_PST));

    // Setup HET
    HETGCR_bit.CLK_MASTER = 0x1; // HET Master Mode
    HETGCR_bit.IGNORE_SUSPEND = 0x1; // Ignore SW BP
       
        // Time slots available = (Hr*Lr)-1 = (2 * 32 )-1 = 63
        // fHR = SYSCLK/Hr, fLr=SYSCLK/(Hr*Lr)    
    HETPFR = 0x00000501;

     HETDIR = 0xFFFFFFFF; // set all HETx as output
     HETDOUT = 0xFFFFFFFF; // clear HET output
     HETGCR_bit.ON = 0x1; //HETGCR  |= 0x1; // Enable HET
   
     HETXOR_bit.HR_XOR_SHARE_0_1=0x0; //HET0 and HET 1 are NOT shared


 //*************************
  // Loop forever.
  while(1)
  {
     volatile unsigned int i;

       GIODOUTA ^= 0xFF; ; // Toggle GIOA4 high and low

       i = 50000;                          // Delay
       do (i--);
       while (i != 0);
 
    
  }
 //*************************
}
--------------------------------------------------------------------------------------------------------

HET_pwm.het

; Init SYSCLK, Foscin = 14.7456Mhz
; Enable peripherals and set clock to SYSCLK, ICLK = SYSCLK
; HET clock = SYSCLK

; Use TMS470R1x HET Reference Guide page 33 as example

A_PIN  .equ 0       ; HET0 is used as output pin
B_PIN  .equ 1       ; HET1 is used as output pin



CN: CNT { next=EA, reg=A, max=22 }

EA: ECMP { next=EB, cond_addr=MA, hr_lr=HIGH, en_pin_action=ON, pin=A_PIN,action=PULSELO, reg=A, data=17, hr_data=19 }
MA: MOV32 { next=EB, remote=EA, type=IMTOREG&REM, reg=NONE, data=17, hr_data=19 }

EB: ECMP { next=CN, cond_addr=MB, hr_lr=HIGH, en_pin_action=ON, pin=B_PIN,action=PULSELO, reg=A, data=5, hr_data=13 }
MB: MOV32 { next=CN, remote=EB, type=IMTOREG&REM, reg=NONE, data=5, hr_data=13 }

-----------------------------------Generate *.c and *.h files-------------------------------------

HET_pwm.c

#include "std_het.h" 

HET_MEMORY const HET_INIT0_PST[5] =
{

     /* A_PIN_0 */
    {
        0x00001600,
        0x00000016,
        0x00000000,
        0x00000000
    },

     /* EA_0 */
    {
        0x00003000,
        0x00102008,
        0x00000233,
        0x00000000
    },

     /* MA_0 */
    {
        0x00003401,
        0x0000000E,
        0x00000233,
        0x00000000
    },

     /* EB_0 */
    {
        0x00000000,
        0x00104088,
        0x000000AD,
        0x00000000
    },

     /* MB_0 */
    {
        0x00000403,
        0x0000000E,
        0x000000AD,
        0x00000000
    }
};

-------------------------

HET_pwm.h

#define HET_CN_0    (e_HETPROGRAM0_UN.Program0_ST.CN_0)
#define HET_EA_0    (e_HETPROGRAM0_UN.Program0_ST.EA_0)
#define HET_MA_0    (e_HETPROGRAM0_UN.Program0_ST.MA_0)
#define HET_EB_0    (e_HETPROGRAM0_UN.Program0_ST.EB_0)
#define HET_MB_0    (e_HETPROGRAM0_UN.Program0_ST.MB_0)


typedef union
{
     HET_MEMORY    Memory0_PST[5];
    struct
    {
        CNT_INSTRUCTION CN_0;
        ECMP_INSTRUCTION EA_0;
        MOV32_INSTRUCTION MA_0;
        ECMP_INSTRUCTION EB_0;
        MOV32_INSTRUCTION MB_0;
    } Program0_ST;

} HETPROGRAM0_UN;

extern volatile HETPROGRAM0_UN e_HETPROGRAM0_UN;

extern const HET_MEMORY HET_INIT0_PST[5];

 

Regards,

Soo

  • Hello,

    Further simulation update:

    I've used the HET Simulator to assemble and simulate the above HET_pwm.het file.

    The HET simulation setting (same as main.c): HET clock =14MHz (note: seems to require integer number, unable to enter 14.7456Mhz), Hr=2, Lr=32, HET0 and HET1 = output, and those pin are not shared, not XOR or not AND.

    The simulator shows that HET0 and HET1 are working fine (figure below). There are PWM signals on pin HET0 and HET1 while the HET clock is running:

    Thus, may be something in main.c that I may have setup wrong? Am I missing something here?

    Any ideas? Thank you for your help!

     

    Regards,

    Soo

  • I read through and did not find anything wrong.

    Can you comment //HETXOR_bit.HR_XOR_SHARE_0_1=0x0; //HET0 and HET 1 are NOT shared. I prefer to set everything before enable HET?

    How do you set up your VCLK2 (the clock source for HET)?

    Can you add some instructions like:

     e_SYSTEM_ST.CLKCNTL_UN.CLKCNTL_ST.VCLK2R_B4 = 1;
     e_SYSTEM_ST.CLKCNTL_UN.CLKCNTL_ST. VCLKR_B4 = 1;

    to configure your VCLK and VCLK2?

    After that, try to toggle another HET pin in the while loop using HETDSET and HETDCLR to see if the HET works or not.

    Regards,

    Haixiao

     

  • Hi Haixiao,

      Thank you very much for your prompt reply!

       I'm using the evaluation kit with chip TMS470R1VF689 (TMP version). Based on TMS470MF0660 datasheet, the HET clock is called VCLK2.

      Correct me if I'm wrong, for the TMS470R1x microprocessor, the HET clock is equal to SYSCLK (SPNU189H: TMS470R1x System Module Reference Guide, page 43). Thus, my HET clock setting -> GCR = 0x00000007; // set SYSCLK = (Foscin * 8)/8, where Foscin = 14.7456Mhz:

       HET clock = SYSCLK = 14.7456MHz

       Yes, I'll try out your suggestions to comment out the HETXOR_bit.HR_XOR_SHARE_0_1, and use HETDSET and HETDCLR to toggle another HET pin. I'll let post the results of my testing.

       I'm not sure whether I can set the VCLK and VCLK2. Of course, I can change the mapping file to include VCLK and VCLK2, but I don't think those registers are defined for TMS470R1x microprocessor (cannot find in the datasheet). Do you mean VCLK = SYSCLK, and VCLK2 = HET clock  = SYSCLK? Am I wrong?

     

     Thanks,

       Soo

  • Soo,

    Please be aware that the TMS470R1x series is not recommended for new designs.  Please see the full 'NRDN' notice here.

    Soon TI will be launching the new TMS470M series of microcontrollers.  This series will feature greater ARM CPU performance and a similar peripherial set to the TMS470R1 Series of microcontrollers.  Please come back soon for more information about the TMS470M Series of microcontrollers.  The product preview for the first two microcontrollers in the TMS470M series is available here: TMS470MF0660x - SPNS157. The TMS470M Series Technical Reference Manual is available here: TMS470M TRM.

    I thought you are using 470M or 570 devices. They have VCLK, VCLK2 and HCLK domains. And VCLK2 is for HET. You are actually using R1x devices. I am not familar with R1x devices. The application note I sent out is for 570 devices. The major difference between R1x and 570 devices are the HR, LR field.

    You have to select the right device name when you do the HET simulation. If this R1x device is not available from the HET list, please try 470M (TMS470M6607). They are not exactly the same but close.

    Regards,

    Haixiao

  • Hi Haixiao,

        Again, thank you very much for your reply!

        Sorry for any confusion may have caused. We're planning to switch to new chip (470M series), but  currently the evaluation kit (close to 470M series) that is available to us is having chip TMS470R1VF689 on it.

        Thanks for confirming that TMS470M6607 is close to TMS470R1x. Yes, for HET simulation, I'm selecting 470M(TMS470M6607) since that is the only HET model that is close to the chip I'm using, TMS470R1x.

     

       Test 1 quick update:

       Commented "HETXOR_bit.HR_XOR_SHARE_0_1=0x0; //HET0 and HET 1 are NOT XOR" --> Both pin HET0 and HET1 still are not toggling.

     

        I'll continue testing based on your other suggestions.

     

    Thanks,

    Soo

  • Hi Haixiao,

      Here is the update of test no. 2:

      Yes, I'm able to toggle the pin HET2 using the HETDSET and HETDCLR commands. 

    -------------modifed main.c-----------------------

    .

    .

    .

      // Loop forever.
      while(1)
      {
         volatile unsigned int i;

         
         
           GIODOUTA ^= 0xFF; ; // Toggle GIOA high and low
           //GIODOUTA_bit.GIODOUT4  ^= 0x1; ; // Toggle GIOA4 high and low

           HETDSET |= 0x00000004 ; //set HET2

           i = 50000;                          // Delay
           do (i--);
           while (i != 0) ;

           HETDCLR |= 0x00000004 ; //clear HET2
          
           i = 50000;                          // Delay
           do (i--);
           while (i != 0) ;
     
      }

    ---------------------------------------------------------------------------

     

    However, HET0 and HET1 still are not toggling, no PWM signal on pin HET0 and HET1.

     

    Regards,

    Soo

  • Soo,

    I checked with our HET expert. One major differece from R1x to 470M:

    You have set the SMCR1 (set >=7 wait states) before you access the HET RAM.

    Please check spnu189h.pdf for how to program the wait states.

    Regards,

    Haixiao

  • Hi Haixiao,

       Yes, it's working now! Thank you very much for all the help!

       I've included the SMCR1 setup in my initialization routine: 

      //Static Memory Control Register 1
      SMCR1    = 0x00000072;    // set the wait states to 7 (min; pg 10 of HET pdf) and data width to be 32-bits 

     

    -------useful documents about SMCRx-------------------------

    1. Just found this out, TMS470R1x Startup Sequence Description, http://focus.ti.com/lit/an/spna079a/spna079a.pdf , where it stated (page 6):

    "SMCR0 controls the program memory access, SMCR1 controls the HET RAM access, and SMCR4
    controls the external flash."

    2. spnu189, http://focus.ti.com/lit/ug/spnu189h/spnu189h.pdf . page 8.

    3. In device datasheet, http://focus.ti.com/lit/ds/symlink/tms470r1vf689.pdf , page 18, SMCR1 is mapped to control HET ram.

     

    Thanks,

    Soo