• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 31 subscribers
  • Views 941 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TM4C1294NCPDT: Tm4c1294 ADC sequencer

Lukasz Huchel
Expert 1420 points
Part Number: TM4C1294NCPDT


Tool/software: Code Composer Studio

Hi,

I have a question regarding the ADC peripheral on tm4c1294 Tiva MCU. There are 2 ADC modules: ADC0 and 1. Each has 4 available sequencers with particular number of sample channels to configure. I use it together with DMA ping-pong mode to use the sampled data for some frequency analysis. 

Here is the thing that I want to make sure about. Is each sequencer SS-H (simultaneus sample hold)? There are 2 ADC modules and each has many multiplexed inputs, if I trigger the ADC lets say with fixed PWM the sampling frequency is per sequencer and will convert all configured channels (up to the one configured as END) of sequencer?

Thanks

  • 0
    TI__Guru 72500 points
    Each ADC module has its own sample and hold register, but the 4 sequencers share a sample and hold. The priority among the four sequences can be set in the ADCSPRI register.
  • 0 in reply to Bob Crosby
    Expert 1420 points
    Hi Bob,

    Thanks for response. Ok, sequencers share one SH circuit. So let's say for sequencer 0 and 8 possible sample channels after each sampling period (the trigger period of PWM in my case) one of the 8 conversions is done. I need 8 sampling periods to fill the FIFO buffer since there is one SH circuit?

    I am using sequencer 0 and all 8 samples multiplexed to the same analog input. I want to make sure that the data buffer is filled in a way I understand it.

    Thank you a lot.
  • 0 in reply to Bob Crosby
    Expert 1420 points

    I couldn't find the explicit answer in the datasheet and results for some sample signals from function generator look like within one sampling period (the trigger frequency) all sequencer channels (8 for me) are sampled. Here is the result:

    -signal is 50Hz sinusoid with offset

    -sampling is 1kHz, should give 20 samples per period

    -all 8 samples of sequencer 0 are multiplexed to the same analog input

     There are 20 "sample groups" per signal 1/50Hz period and "each sample" group has 8 members with pretty much one value. It looks like sequencer was able to sample and hold 8 values.

    Thank you

  • 0 in reply to Lukasz Huchel
    TI__Guru 72500 points
    The ADC converter is very versatile. When you trigger a sequence, the converter samples and converts all channels in that sequence one after the other as quickly as possible. That is why you see 8 samples taken very nearly at the same time. If you want 1KHz samples, simply configure the sequence to only sample the channel one time.
  • 0 in reply to Bob Crosby
    Expert 1420 points

    Thank you Bob, I wanted to bu sure about principals of operation for internal ADCs' of this MCU.

    Thanks.