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CCS/TMS570LS3137: (Error -242 @ 0x0) A router subpath could not be accessed. (Error -2064 @ 0x0) Unable to read device status.(Error -1170 @ 0x0) Unable to access the DAP.

Part Number: TMS570LS3137


Tool/software: Code Composer Studio

Hi,

I use the customized board with the following tools:

1. CCS Version: 7.3.0.00019  with the gcc compiler version : TI v16.12.0.STS

2. Texas instruments XDS100v3 USB Debug Probe

I get the following error when programming the TMS, causing the CCS to stop erasing/program load. 

CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0 due to System Reset
CortexR4: Trouble Setting Breakpoint with the Action "Remain Halted" at 0x80004c0: (Error -242 @ 0x0) A router subpath could not be accessed. The board configuration file is probably incorrect. (Emulation package 7.0.48.0)
CortexR4: Breakpoint Manager: Retrying with a AET breakpoint
CortexR4: Can't Run Target CPU: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
CortexR4: Trouble Halting Target CPU: (Error -2064 @ 0x0) Unable to read device status. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
CortexR4: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)

... 
CortexR4: Unable to determine target status after 20 attempts
CortexR4: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
CortexR4: File Loader: Memory write failed: Cannot disable hardware breakpoint while the target is halted. Halt the target and try again

The following is the output of the programmer test (verify connection):

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\...
CCS\ti\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusbv3.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 64 - 01 00 500.0kHz O good value measure path length
2 64 + 00 00 1.000MHz [O] good value apply explicit tclk

There is no hardware for measuring the JTAG TCLK frequency.

In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 6 bits.
The JTAG DR length was 1 bits.

The IR/DR scan-path tests used 2 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 1.000MHz as the highest frequency.
The IR/DR scan-path tests used 1.000MHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

Even if the scan test has succeeded, the programmer won't load the code. I also get the error code as below:

Error connecting to the target:
(Error -233 @ 0x0)
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.
(Emulation package 7.0.48.0)

please note that after some successful attempts of loading the program, I get the above error. 

Kindly, suggest me on the same.

Thanks,

Vivek

  • Vivek,

    It looks like the code you programmed is making the part enter an exception state repeatedly. This prevents the CPU from entering a debug state, resulting in the behavior you observe. You need to try to erase the part, assert and release nRST to see if the erase command is able to halt the CPU and erase the flash.
  • Sunil Oak said:
    Vivek,

    It looks like the code you programmed is making the part enter an exception state repeatedly. This prevents the CPU from entering a debug state, resulting in the behavior you observe. You need to try to erase the part, assert and release nRST to see if the erase command is able to halt the CPU and erase the flash.

    Hi Sunil,

    I get the below error frequently whenever i try to load the program:

    Error connecting to the target:
    (Error -233 @ 0x0)
    The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
    An attempt to scan the JTAG scan-path has failed.
    The target's JTAG scan-path appears to be broken
    with a stuck-at-ones or stuck-at-zero fault.
    (Emulation package 7.0.48.0)

    I need to restart the TMS and the JTAG programmer every now and then to load.

    I tried releasing the nRST, but the erase command is not able to halt the CPU. 

    Thanks 

    vivek

  • Vivek,

    You may need to attempt to erase the part multiple times playing with the reset timing, allowing the JTAG emulator to halt the CPU and then allowing erase of Flash memory.

    Regards,
    Sunil