EK-TM4C123GXL: External Serial Nor Flash + SSI + uDMA

Hi Charles,

I use cmd_buf for RX because I don't want to create an extra variable to store the returned bytes from cmd / addr transfer. Also, since we receive the same amount of data bytes as we transmit, therefore both TX and RX share the same transfer size of cmd_count.

Btw, is there a reason behind why it works out when I put everything in one DMA transfer and fails when I break it down into multiple DMA transfer? (as shown in the original post with screenshots)
Or I guess I should ask if there is anything in my DMA setup or configuration that causes problems to the transfer.

In the mean time, I will look into scatter-gather method and keep the post updated.

Thanks,

Jacky

Charles Tsai said:

It seems to me that the uDMA peripheral scatter-gather is well suited for your application requirement even though your current setup should work too if all you want is to read the manufacturing and device id.

Are you saying if I were to read / write large amount of data, then my method will not be as efficient?

Thanks,

Jacky

Hi Charles,

I intend to do read/write/erase operations on the flash as well. The ID reading is just to make sure my basic SSI transfer function works.

What would you suggest If I plan to do so? Could I have done read/write/erase using the basic mode?

Thanks,

Jacky

Charles Tsai said:

Why do you want to break it into two different DMA transfers as shown in your code?

So the reason that I want to break it into two different DMA transfers is that I don't want the return data bytes from sending the cmd / addr bytes to mess with my destination data buffers. In my case for example, the flash read function has to be like the following, (takes in three parameters from the user and returns void. The content within the function can be modified just as long as the read function parameter and return type remains)

void my_spi_read(uint32_t addr, uint32_t num_byte, uint8_t *dst) {
    uint8_t cmd[4];

    cmd[0] = WB_READ_DATA;
    cmd[1] = (addr >> 16) & 0xFF;
    cmd[2] = (addr >> 8) & 0xFF;
    cmd[3] = (addr >> 0) & 0xFF;

    g_rx_dst_inc = UDMA_DST_INC_8;
    g_tx_src_inc = UDMA_SRC_INC_NONE;

    uint8_t tx_dummy = 0x00;

    ssi_transfer(cmd, 4, &tx_dummy, num_byte, dst, num_byte);

    while (chip_busy() & 1);
}

My thought was, if I put the cmd / addr transfer in a separate DMA transfer, then my destination data buffer will not contain the return bytes from sending cmd / addr.

I want the user of this function to just enter a starting address within the flash, the number of bytes to read and provide a destination data buffer (with buffer size = number of bytes to read) to store the data read.

Eg. user wants to read 256 bytes starting at addr 0x00, then the destination data buffer will only contain 256 bytes of data (not containing return bytes from sending cmd / addr)

I hope this makes my problem clearer. Do you think scatter-gather method is better in this case (maybe have cmd/addr as one task and the rest as another task?) or do you have other ways to go about this? If so, how would you approach this problem?

Thank you very much for your help!

Regards,

Jacky

Hi Charles,

So I think my code in the earlier post did not work out is due to the DMA being in basic mode which leaves a dead time between reload and next transfer?

Regards,

Jacky

Hi Charles,

I have setup two primary structures (one for cmd / addr and one for actual data) and two alternate structures (one for cmd / addr and one for actual data) for the DMA transfer and my communication with the flash worked out fine.

Assuming my length of data will not exceed 1024, which means I will never reload, what is the best way to properly exit the DMA? So far, I am checking the SSIRX channel of the alternate structure for stop mode signal in the ISR like so:

void SSI0IntHandler(void) {
    GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_PIN_2); // indicate ISR entry

    uint32_t ui32Status;
    uint32_t ui32Mode;

    ui32Status = SSIIntStatus(SSI0_BASE, 1);

    SSIIntClear(SSI0_BASE, ui32Status);

    ui32Mode = uDMAChannelModeGet(UDMA_CHANNEL_SSI0RX | UDMA_ALT_SELECT);

    // Data transfer done, pull CS high
    if (ui32Mode == UDMA_MODE_STOP) {
        IntDisable(INT_UDMAERR);
        IntDisable(INT_SSI0);
        chip_select(GPIO_PIN_3);
    }

    GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_2, ~GPIO_PIN_2); // indicate ISR entry
}

Is this a safe way to do or should I check if all channels are at stop mode before actually stopping (by pulling the SS line high)?

Thanks,

Jacky

Hi Charles,

Ok. I think I am not understanding DMA ping-pong mode properly. Here is my current setup:

TX (UDMA_CHANNEL_SSI0TX)                                 RX (UDMA_CHANNEL_SSI0RX)

Primary Struct (Sending cmd/addr)    ------------>    Primary Struct (Receiving return bytes from sending cmd/addr)  

Alternate Struct (Sending N bytes of data) ------>   Alternate Struct (Receiving N bytes of data)

Here is my code for the DMA setup:

void ssi_transfer(uint8_t *cmd_buf, uint32_t cmd_count, uint8_t *tx_buf,
                  uint8_t *rx_buf, uint32_t data_count) {

    //
    // Enable the uDMA interface for both TX and RX channels.
    //
    SSIDMAEnable(SSI0_BASE, SSI_DMA_RX | SSI_DMA_TX);

    //*************************************************************************
    //uDMA SSI0 RX
    //*************************************************************************

    //
    // Put the attributes in a known state for the uDMA SSI0RX channel.  These
    // should already be disabled by default.
    //
    uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI0RX,
                                UDMA_ATTR_USEBURST |
                                UDMA_ATTR_ALTSELECT |
                                (UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK));

    //
    // Configure the control parameters for the primary control structure for
    // the SSIORX channel.
    //
    uDMAChannelControlSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT,
                          UDMA_SIZE_8 | UDMA_SRC_INC_NONE |
                          UDMA_DST_INC_8 | UDMA_ARB_4);

    //
    // Configure the control parameters for the alternate control structure for
    // the SSIORX channel.
    //
    uDMAChannelControlSet(UDMA_CHANNEL_SSI0RX | UDMA_ALT_SELECT,
                          UDMA_SIZE_8 | UDMA_SRC_INC_NONE |
                          g_rx_dst_inc | UDMA_ARB_4);

    //
    // Set up the transfer parameters for the SSI0RX Channel (primary)
    //
    uDMAChannelTransferSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(SSI0_BASE + SSI_O_DR),
                           cmd_buf,
                           cmd_count);

    //
    // Set up the transfer parameters for the SSI0RX Channel (alternate)
    //
    uDMAChannelTransferSet(UDMA_CHANNEL_SSI0RX | UDMA_ALT_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(SSI0_BASE + SSI_O_DR),
                           rx_buf,
                           data_count);


    //*************************************************************************
    //uDMA SSI0 TX
    //*************************************************************************

    //
    // Put the attributes in a known state for the uDMA SSI0TX channel.  These
    // should already be disabled by default.
    //
    uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI0TX,
                                UDMA_ATTR_ALTSELECT |
                                UDMA_ATTR_HIGH_PRIORITY |
                                UDMA_ATTR_REQMASK);

    //
    // Configure the control parameters for the SSI0 TX.
    //
    uDMAChannelControlSet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT,
                          UDMA_SIZE_8 | UDMA_SRC_INC_8 |
                          UDMA_DST_INC_NONE | UDMA_ARB_4);

    //
    // Configure the control parameters for the SSI0 TX.
    //
    uDMAChannelControlSet(UDMA_CHANNEL_SSI0TX | UDMA_ALT_SELECT,
                          UDMA_SIZE_8 | g_tx_src_inc |
                          UDMA_DST_INC_NONE | UDMA_ARB_4);

    //
    // Set up the transfer parameters for the uDMA SSI0 TX channel.  This will
    // configure the transfer source and destination and the transfer size.
    // Basic mode is used because the peripheral is making the uDMA transfer
    // request.  The source is the TX buffer and the destination is the SSI0
    // data register.
    //
    uDMAChannelTransferSet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT,
                           UDMA_MODE_PINGPONG,
                           cmd_buf,
                           (void *)(SSI0_BASE + SSI_O_DR),
                           cmd_count);

    uDMAChannelTransferSet(UDMA_CHANNEL_SSI0TX | UDMA_ALT_SELECT,
                           UDMA_MODE_PINGPONG,
                           tx_buf,
                           (void *)(SSI0_BASE + SSI_O_DR),
                           data_count);

    // Send command / address bytes and pop out return bytes
    chip_select(~GPIO_PIN_3);

    //
    // Now both the uDMA SSI0 TX and RX channels are primed to start a
    // transfer.  As soon as the channels are enabled, the peripheral will
    // issue a transfer request and the data transfers will begin.
    //
    uDMAChannelEnable(UDMA_CHANNEL_SSI0RX);
    uDMAChannelEnable(UDMA_CHANNEL_SSI0TX);

    // Wait until the SSI chip select de-asserts, indicating the end of the
    // transfer.
    while (!(GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_3) & GPIO_PIN_3));
}

Charles Tsai said:

My only question is why do want to setup two different channels? I thought one ping-pong channel is enough where the primary transfers the cmd/addr while the alternate transfers the data.

I am not exactly understanding how this is going to work using just one channel. Are you saying one struct is able to do both transmit/receive? Do I re-setup the transfer in the ISR? Please enlighten me!

Regards,

Jacky

Hi Charles,

The N bytes is variable. My goal is to make flash read, write, erase ... etc APIs utilizing DMA transfer in order to reduce CPU load. If it works out well, I am even considering using those APIs on a flash file system!

For example my flash read API would have the user input the starting address for the read (addr), the number of bytes to read (num_bytes) as well as providing a destination buffer to store the data read (dst). 

void my_spi_read(uint32_t addr, uint32_t num_byte, uint8_t *dst) {

    uint8_t cmd[4];

    cmd[0] = WB_READ_DATA;
    cmd[1] = (addr >> 16) & 0xFF;
    cmd[2] = (addr >> 8) & 0xFF;
    cmd[3] = (addr >> 0) & 0xFF;

    g_rx_dst_inc = UDMA_DST_INC_8;
    g_tx_src_inc = UDMA_SRC_INC_NONE;

    uint8_t tx_dummy = 0x00;

    ssi_transfer(cmd, 4, &tx_dummy, dst, num_byte);

    while (chip_busy() & 1);
}

In the case that the number of bytes exceeds 1024, I will simply reload in the ISR.

So I guess, my DMA setup is fine for what I am trying to do? Do you see potential problems with where I am heading to that I should keep an eye on?

Regards,

Jacky