TMS570LC4357: ESM error signaling

Hi TIDR,

I will look into this and get back to you today. How are they measuring the delay?

Hi Dipa,

The Cortex-R5 CPU is capable of issuing multiple instructions, and this set of instructions meets all the requirements defined in the Cortex-R5F TRM for dual-issue of instructions. The "dsb" blocks all further data fetches until the "ldr" instruction completes the access from the L2 flash memory (OTP read for double-bit error). However, the other subsequent instructions are fetched (after the "dsb" instruction has gone past the decode stage of the pipeline) and executed as there is no dependency on the "ldr" instruction. The delay the customer is observing is a cumulative effect of time taken to execute the "ldr" instruction (through the 8-stage CPU pipeline), time taken for the access to "reach" the flash memory through the interconnect, time taken for the returned data and ECC to travel back to the CPU, and finally the time taken to signal the error to the ESM.

Regards,
Sunil

Hi Sunil

Thanks for the response.

The ARM documentation says the following about DSB:

 

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/CIHGHHIE.html

 

Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:

 

All explicit memory accesses before this instruction complete.

 

All Cache, Branch predictor and TLB maintenance operations before this instruction complete.

 

So, your comment that instructions gone past the decode pipeline will execute if not dependent on the ldr instruction doesn't seem to be called out here. Wouldn't the "dsb" instruction  remain in execute stage (and thus stall the pipeline) until the access from the L2 flash memory completes ("All explicit memory accesses..."). Subsequent instructions may be fetched / decoded prior to L2 flash memory access completion, but will not be executed until after access completion, because "dsb" is still in execute stage until after access completion.

 

Given the sequence of instructions would there be any reason for this delay to be variable? The customer is counting delay based on number of NOPs before the bit is set.

 

Thanks!

 

Hi Dipa,

I was wrong when I said that the subsequent instructions are allowed to be fetched and executed past the "DSB". As the customer stated, the LDR instruction must completely execute before the pipeline is allowed to proceed.

Also, this uncorrectable error on the AXI-bus access is signaled directly to the ESM. I am trying to find out any timing information about indicating this error on the CPU's event bus. The customer can also use the PMU to better monitor the timing of the event bus signaling.

Regards,

Sunil

Hi Sunil,

Any update on this to explain what causes the delay in ESM signaling?

Rgds