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Original question:

TM4C1294KCPDT: Analog comparator C0+ threshold

TM4C1294KCPDT: Analog comparator C0+ threshold

Genatco
Guru 55913 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: INA303, INA240

Is it possible that the PWM module generators MnFaults GPIO inputs when internally OR'd are effecting analog comparators shared C0+ (pin0) or Cn- input threshold levels?

Oddly the voltage trip threshold seems to increase from C0- to C1- by over 200mv and over 500mv C1- to C2- as the MnFault inputs are enabled consecutively. So each analog comparators XOR GPIO output seemingly should be (Open Drain) when a single PWM0 generator can or might internally OR multiple fault sources together. 

Seemingly the fault source OR is necessary so any single MnFault will trip fault or interrupt any GENS part of the OR'd fault structure. This is so any random fault arriving on any MnFault input pin disables the PWMENABLE register in the output control block.  

Tivaware call to OR multiple generators for analog comparators XOR outputs being connected to PWM module MnFault inputs. 

   /* Configure (OR'd) extended fault group-0 interrupt sources for M0Fault pins.
    * Assertion to PWM inactive TFaultMax = 40ns, (24ns+1PWMCLK) */
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_0, PWM_FAULT_GROUP_0,
    				(PWM_FAULT_FAULT0|PWM_FAULT_FAULT1|PWM_FAULT_FAULT2));
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_1, PWM_FAULT_GROUP_0,
    				(PWM_FAULT_FAULT0|PWM_FAULT_FAULT1|PWM_FAULT_FAULT2));
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_2, PWM_FAULT_GROUP_0,
    				(PWM_FAULT_FAULT0|PWM_FAULT_FAULT1|PWM_FAULT_FAULT2));

 

  • 0
    TI__Guru 72500 points
    No, that does not seem at all likely. More likely the offset is from noise induced on the input to the comparators caused by currents being switched by the PWM.
  • 0 in reply to Bob Crosby
    Guru 55913 points

    Hi bob,

    Perhaps that is not entirely true and CB1 was partly onto why. Typical comparators with open collector outputs need a pull up resistor but he stopped short connecting how TM4c129x analog comparators accomplish that OR'd logic in light of dumping into MnFaultn inputs.

    Indeed when the TM4C analog comparator outputs are configured OD for MnFaultn OR'd inputs with WPU the threshold millivolt level of C2- is greatly reduced as the last PWM GEN OR'd. Seemingly TIDA-0778 engineer points out the three INA303 fault comparators OD outputs are OR'd into 1 fault line for a reason.

    The question remains what to do with the unused floating MCU pins of each comparators partner Cn+ inputs when C0+ PINO GPIO port C6 is the external shared threshold? How are the three floating MCU pins effecting the analog comparator block in light of PWM noise?

  • 0 in reply to Genatco
    Guru 55913 points

    The external +VREF threshold for C2- input was reduced from over 3.0v to roughly 2.52v after Co2 output pin type was made OD and MnFault2 inputs WPU. Respectively all three analog comparator COn outputs were made OD and MnFault inputs WPU. This resolved a huge problem of incorrect threshold tripping mostly in the last GEN2 MnFault being (OR'd) into Co2 output.

    Apparently GPIO push pull outputs when (OR'd) together cause current flow in co-partner outputs, back feeding through the internal silicon gates. There is still a small amount of trip hedging on C2- input randomly below the lower 2.5v threshold but far less than before. A 500mv input threshold improvement is worth investigating how come!!

    That said it would seem as if we should have tied unused analog comparator inputs (Cn+) to ground. Yet the datasheet electrical section makes no comment about these pins. We left them floating, in hind sight it may have been better to ground them? And now perhaps simply solder comparator MCU pins together? That is tie each unused (C+) input to (C-) active input to stop current flowing in the MCU pin?  How might these unused C1+/C2+ input pins also effect input threshold tripping from undesired phantom current flow?   

  • 0 in reply to Genatco
    TI__Guru 72500 points
    Hi BP101,
    Yes, now I understand. Having push-pull outputs tied together will cause high currents when there is a drive conflict. Those currents can exceed the GPIO current restrictions of section 27.3.2. This in tern will lead to offsets of all levels. This is likely to be most noticeable in the analog comparators and the A to D.
  • 0 in reply to Bob Crosby
    Guru 55913 points
    Hello Bob,

    Perhaps there should be two Tivaware calls GPIOPinTypeComparatorOutput(). Obviously this issue has plagued our project for some time now but only recently has it become clear why.

    Oddly the C2- input level is a bit lower than C0-/C1- by 18mv, all being INA240 monitors sharing 1.225v precision reference. Perhaps the other configuration has stressed the C2- input or C2+ floating is making odd current flow?