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TMS570LS1224: How to make SPI interrupts work?

Varun Malladi
Intellectual 270 points
Part Number: TMS570LS1224
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am trying to communicate SPI2 master and SPI4 as slave. I am trying to call the function SpiSendData() which has interrupt. The sys_startup.c has vim_init() and I added vim_enable_interrupt function so Spi2 high and low, Spi4 high and low have interrupts enabled in the main function. My interrupt line is INT0. Spi2 transmit interrupt is high so spi2HighLevelInterrupt(void) has to be called but I am not able to get into interrupt function as its not stopping at the breakpoint. Is there anything that I am missing?

Thanks

Varun

  • 0
    TI__Guru**** 196776 points

    Hello,

    1. LS1224 BGA package has SPI2 and SPI4, but LS1224 QFP package doesn't have SPI2.

    2. Since you enable the SPI2/SPI4 interrupt in VIM manually, please make sure the SPI2 High level ISR is programmed to VIM channel 17 (address is 0x48), and SPI4 High level ISR is programmed into VIM Channel 49 (address is 0xC8).

    3. SPI2_LVL, SPI4_LVL, SPI2_INT0, and SPI2_INT0 are configuredd correctly. The bit value of 0 in SPI_LVL means the interrupt is mapped to HIGH LEVL (line 0) 

    4. Did you get RX Interrupt in SPI4 side?

  • 0 in reply to QJ Wang
    Intellectual 270 points

    Hi,

    Sorry, on my board it says it is TMS570LS1224CPGE. So in HALCOGEN it shows I 1224PGE so if I select it, there is no SPI2.

    Anyway I want to do a loop back test, all I want is to get into interrupt. So I kept SPI4 loop back bit in GCR1 set, Clock set, Master set. 

    I called InterruptEnable Funtion for 49 in main function and then spiSendData with interrupt. 

    How do I now program SPI4 High level into VIM 49? I set them in Halcogen enabling them in Tab VIM Channel 32-63. All interrupts are high level for now. 

    And no, I am not able to get into any ISR at all. I should at least get into Tx interrupt in SPI4.I just want to understand how to get into ISR. Should I write any assembly language writing CPSR? 

    Regards

    Varun

  • 0 in reply to QJ Wang
    Intellectual 270 points

    Can you please explain what does sys_intvecs.asm do and sys_svc.asm do? Not understanding how do they work? Should I have to do anything with those files? Why or why not? Sorry I am newbie lots of questions. 
    Thanks!
    6215.sys_intvecs.asm3125.sys_intvecs.asm

  • 0 in reply to Varun Malladi
    TI__Guru**** 196776 points
    Hello Varun,

    1. At CPU level, call _enable_IRQ() to enable IRQ interrupt. This intrinsic function clears the I bit in CPSR register.
    2. At VIM level, enable the channels for SPI2 High and SPI4 High. If the HALCoGen doesn't this module (for example SPI2), please enable it manually:
    1. sys_vim.c: use SPI2 ISR function (spi2HighLevelInterrupt) for channel 17 in s_vim_init[96U] ={...}
    2. Set channel 17 (SPI2 Hig) of vimREG->REQMASKSET0 = ...
    3. At SI module level: enable the TX and RX interrupt by setting the bit 8 and bit 9 of SPIINT0 register
  • 0 in reply to QJ Wang
    TI__Guru**** 196776 points
    Hello Varun,

    the sys_intvecs.asm defines the exception vector table for the device. A fault or error event that is considered serious enough to require that program execution is interrupted. Examples include attempting to perform an invalid memory access, external interrupts, and Undefined instructions. When an exception occurs, normal program flow is interrupted and execution is resumed at the corresponding exception vector.

    Cortex-Rx device has 7 exceptions:
    1. reset
    2. undefine
    3. SVC
    4. Prefetch
    5. data abort
    6. IRQ
    7. FIQ