Unable to find NHET RAM 64-Bit Write Access feature within TRM

Hello Haixiao,

Can you please let me know how do I update CONTROL and DATA Field of MOV64 NHET Instruction using 64-Bit WRITE Cycle to NHET RAM?

In the older HET, there was some SHADOW Register concept and hence two successive 32-Bit Write Cycle will update the CONTROL and DATA Field of MOV64 HET Instruction in a single shot.

I am trying to perform the similar function in NHET and couldn't find any information.

Now you are telling me that NHET RAM supports only 32-Bit WRITE Cycle.

Then how does MOV64 single shot CPU update of CONTROL and DATA Field will work?

Please help soon.

Thank you.

Regards

Pashan

Pashan,

I have not got feedback from our design team. Based on all the documents I have, it can only support 32-bit write.

As a work around, you can use:

DJZ

MOV64

.....

At beginning and during normal running, the datafield of DJZ is zero, therefore, the NHET bypasses the MOV64 instruction.

After you complete updating both the control field and data field in the MOV 64 instruction from CPU side, set the data field of DJZ to 1.

Then, in the next loop, the MOV64 bit will be excuted.

Regards,

Haixiao

Hello Haixiao,

Did you hear any news about the Coherent 64-Bit WRITE to CONTROL/DATA Fields of MOV64 by CPU to NHET RAM?

Because your work-around doesn't always work as DJZ parameter is not always tunable.

Please ask NHET experts about DATA Coherency issue.

Thank you.

Regards

Pashan

Pashan,

Our design team said that the 64bit read was supported by the shadow register. However, the shadow register is not  involved in the write process.

I will check the application expert to see if we have some work around.

Regards,

Haixiao

Hello Haixiao,

In you last reply you said:

"I will check the application expert to see if we have some work around."

Any idea about the final answer from NHET Design Team?

Did they miss that DATA Coherency Issue for MOV64 CONTROL/DATA Field by mistake or intentional omission?

What is the final result of their analysis as that feature was present in TMS470R1x HET [spnu199d.pdf]?

Thank you.

Regards

Pashan

Meanwhile, our group received same question from TI field applications.

Our design group confirmed NHET does NOT support 64-bit write.

Here is the answer from our applications group (This workaround of course increases HET RAM utilization ):

The NHET doesn’t support 64-bit writes. I think the reason why this feature was removed was that it was an awkward SW handling with disabling interrupts or DMA, writing a control register bit, updating the MOV64, then writing the control register bit again and enabling interrupts/DMA.

 Here’s a workaround for the issue. The idea is that the MOV64 only gets executed when the main application tells it to be executed.

 L00:      DJZ {next = L01, cond_addr = L02, data = 0}

L01:      MOV64 …

L02:      ….

The NHET will execute L00, L02 while the data field of the DJZ is 0, thus bypassing the MOV64. Before the CPU updates the MOV64 it can read the DJZ data field to make sure that the MOV64 is not executed (DJZ data field has to be ‘0’). Once the CPU has updated the MOV64 control and data fields, the CPU has to write a ‘1’ into the data field of the DJZ. With this the program execution will be L00, L01, L02 while the DJZ data field is non-zero. Once the DJZ has decremented to ‘0’ again, it will bypass the MOV64.

 Regards,

Haixiao