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Original question:

TMS570 Interrupts + ADC & DMA

CCS/TMS570LC4357: DMA SW not triggering in TMS570LC43x Hercules Development Kit (HDK)

Bijo John
Prodigy 140 points
Part Number: TMS570LC4357

Tool/software: Code Composer Studio

Hi,

We are trying to check the dma feature using TMS570LC43x Hercules Development Kit (HDK).

The MibSPI and SCI DMA transfer using HW trigger is working. But dma transfer using SW trigger is not working.

We want to verify the SW trigger DMA and the DMA chaining functionality.

The code we are using to test the feature is attached.

Could you please help.

Thanks1222.dmaregister.txt

  • 0
    TI__Guru**** 196736 points

    Hello Bijo,

    The DAM of TMS570LC43x devices has two master ports: PortA and PortB (each 64-bits wide). The selection for the port should be made using the table mentioning the port to be used for each address region.

    From my understanding of your code, you want to move data from one location of L2 SRAM to another location of the L2 SRAM. The dmaCTRLPKT.PORTASGN should be 0x2 rather than 0x4.

  • 0 in reply to QJ Wang
    Prodigy 140 points

    Hi Wang,

    Thanks for your reply. We updated the PORTASGN as 0x2 but still the DMA transfer doesn't happen.

    I am attaching the updated code and dma register values.

    Do you have any example code to check the dma chaining functionality ? We are mainly trying to test the dma chaining functionality.

    Thanks. 

    3527.dmreg.txt

    0247.HL_sys_main.c

  • 0 in reply to Bijo John
    Intellectual 310 points
    Hi Wang

    Can you please check why its happening ?, is there any sample code for chain DMA.
  • 0 in reply to QJ Wang
    Prodigy 140 points
    Hi Wang,
    Could you please provide an example for the dma chaining .

    Thanks.
  • 0 in reply to Bijo John
    TI__Guru**** 196736 points
    Hi Bijo,

    The chain bit field in CHCTRL is the next channel to be triggered: 1 is DMA_CH0, 2 is DMA_CH1. In your setting, the channel 9 should be triggered after channel 8.

    I will work out an example project for you
  • 0 in reply to QJ Wang
    TI__Guru**** 196736 points

    Hello Bijo,

    The following code is tested without any problem. 

    int main(void)
    {
    /* USER CODE BEGIN (3) */
    uint32 src0[transfer_size] = {0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888};
    uint32 src1[transfer_size] = {0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, 0xffffffff, 0x12345678};
    uint32 src2[transfer_size] = {0x11223344, 0x55667788, 0x99aabbcc, 0xddeeff00, 0x12345678, 0x13579bdf, 0x2468ace0, 0x87654321};

    uint32 dest0[transfer_size] = {0};
    uint32 dest1[transfer_size] = {0};
    uint32 dest2[transfer_size] = {0};

    /* enable IRQ interrupt */
    _enable_IRQ();
    dmaEnable();

    /* - configuring dma control packets */
    g_dmaCTRLPKT.SADD = (uint32_t)src0; /* source address */
    g_dmaCTRLPKT.DADD = (uint32_t)dest0; /* destination address; starting address of TG0 */
    g_dmaCTRLPKT.CHCTRL = DMA_CH1 + 1; /* channel control */
    g_dmaCTRLPKT.FRCNT = F_COUNT; /* frame count */
    g_dmaCTRLPKT.ELCNT = E_COUNT; /* element count */
    g_dmaCTRLPKT.ELDOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT.ELSOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT.FRDOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT.FRSOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT.PORTASGN = PORTA_READ_PORTA_WRITE;
    g_dmaCTRLPKT.RDSIZE = ACCESS_32_BIT; /* read size */
    g_dmaCTRLPKT.WRSIZE = ACCESS_32_BIT; /* write size */
    g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER ; /* transfer type */
    g_dmaCTRLPKT.ADDMODERD = ADDR_INC1; /* address mode read */
    g_dmaCTRLPKT.ADDMODEWR = ADDR_INC1; /* address mode write */
    g_dmaCTRLPKT.AUTOINIT = AUTOINIT_OFF; /* autoinit */

    // setting dma control packets for receive
    dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT);

    /* - configuring dma control packets */
    g_dmaCTRLPKT.SADD = (uint32_t)src1; /* source address */
    g_dmaCTRLPKT.DADD = (uint32_t)dest1; /* destination address; starting address of TG0 */
    g_dmaCTRLPKT.CHCTRL = DMA_CH2 + 1; /* channel control */
    g_dmaCTRLPKT.FRCNT = F_COUNT; /* frame count */
    g_dmaCTRLPKT.ELCNT = E_COUNT; /* element count */
    g_dmaCTRLPKT.ELDOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT.ELSOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT.FRDOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT.FRSOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT.PORTASGN = PORTA_READ_PORTA_WRITE;
    g_dmaCTRLPKT.RDSIZE = ACCESS_32_BIT; /* read size */
    g_dmaCTRLPKT.WRSIZE = ACCESS_32_BIT; /* write size */
    g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER ; /* transfer type */
    g_dmaCTRLPKT.ADDMODERD = ADDR_INC1; /* address mode read */
    g_dmaCTRLPKT.ADDMODEWR = ADDR_INC1; /* address mode write */
    g_dmaCTRLPKT.AUTOINIT = AUTOINIT_OFF; /* autoinit */

    // setting dma control packets for receive
    dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT);

    /* - configuring dma control packets */
    g_dmaCTRLPKT.SADD = (uint32_t)src2; /* source address */
    g_dmaCTRLPKT.DADD = (uint32_t)dest2; /* destination address; starting address of TG0 */
    g_dmaCTRLPKT.CHCTRL = 0; /* channel control */
    g_dmaCTRLPKT.FRCNT = F_COUNT; /* frame count */
    g_dmaCTRLPKT.ELCNT = E_COUNT; /* element count */
    g_dmaCTRLPKT.ELDOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT.ELSOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT.FRDOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT.FRSOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT.PORTASGN = PORTA_READ_PORTA_WRITE;
    g_dmaCTRLPKT.RDSIZE = ACCESS_32_BIT; /* read size */
    g_dmaCTRLPKT.WRSIZE = ACCESS_32_BIT; /* write size */
    g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER ; /* transfer type */
    g_dmaCTRLPKT.ADDMODERD = ADDR_INC1; /* address mode read */
    g_dmaCTRLPKT.ADDMODEWR = ADDR_INC1; /* address mode write */
    g_dmaCTRLPKT.AUTOINIT = AUTOINIT_OFF; /* autoinit */

    // setting dma control packets for receive
    dmaSetCtrlPacket(DMA_CH2, g_dmaCTRLPKT);

    dmaSetChEnable(DMA_CH0, DMA_SW); /* Enable DMA channel */
    dmaSetChEnable(DMA_CH1, DMA_HW);

    dmaSetChEnable(DMA_CH2, DMA_HW);

    while ((dmaREG->HWCHENAS & 0x07) != 0x0);

    while(1); /* loop forever */

    /* USER CODE END */

    return 0;
    }