TMS570LC4357: Are any TMS570LC4357 registers not reset after a PORRST?

Hello,

On a nPORRST reset, most of the registers get reset to its default values. Some error registers (for example, double bit ECC error addr register (UERRADDR)). After a power-on reset, the contents of those registers will be unpredictable.

After a power-on reset, the contents of the SRAM is unknown. A hardware auto-initialization can be performed so that there is no ECC error.

After a power-on reset, CPU internal registers are not guaranteed to be in the same state for both the CPUs. Any difference in the two CPUs’ outputs is flagged as a fault of a high-severity level. Therefore, the CPU internal core registers need to be initialized to a predefined state before any function call is made.

Hello QJ,

Thank you for following up on my question. I would like to dig into this a little further to make sure that my understanding is complete.

First, I should have made clear earlier when I said "PORRST" that I meant what the Hercules 4357 does in response to the nPORRST input having been held low for at least the minimum required time. (Incidentally, we've connected a TPS65381a's NRES output to our 4357's nPORRST input.)

My understanding is that when executing code immediately after power has been initially applied to the 4357 (and the TPS65381a has released our nPORRST input), then everything which is reset by the 4357's nPORRST logic will be in a known state, and that everything else (including SRAM) will be in an unknown / unreliable state.

My understanding is that after any further nPORRST cycles (if power has been continuously good throughout) that the SRAM contents will contain whatever it had prior to the nPORRST (is this independent of how long nPORRST was low? what if it was low for several seconds?), some? most? CPU & FPU registers will be unreliable, and that _most_ other registers will be reset by the nPORRST logic.

It is these "most other registers" that I am particularly interested in. There are, after all, rather a lot of them. Are there _any_ registers (CPU, FPU, CP15, or TI config/peripheral) that reliably maintain their state across a nPORRST boundary? (If, again, power has been good throughout.)

You mentioned something about the UERR_ADDR registers. The 4357's technical reference manual specifies that they are 0 "after asynchronous reset on power-on reset", which I assume includes nPORRST. Are you saying that those registers are reset to 0 by a nPORRST, but if an access to corrupted SRAM has been attempted prior to any code reading UERR_ADDR, then UERR_ADDR will not be 0?

--thx