I am using the LIN/SCI device in SCI / UART mode.
Wrting a seqeunce of 3 bytes to the TD register, only the last one is transmitted over the line (scope).
It seems as if the TX RDY flag in the SCIFLR register is never CLEARED.
As i am polling the TX RDY flag before writing the next byte to the TD, obviously the last of the sequence of 3 bytes overwrites the precedent ones in the TD register and only the last one gets transmitted.
I checked the assembly code to verify that the FLR (FFF7E41C) is read out and compared (0x100 - bit 8 - TX RDY) in fact.
See the code below: The body of the while loop (waiting as long as TX RDY == 0) is never entered - verified in the debugger and by counter variables.
Only busy waiting via a counter (u16waitCnt) leads to the correct behaviour, i.e. all 3 characters on the line.
Btw. the solution shall work without interrupts.
Thank you,
Michael
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void XX_InitPriv(void) { sciREG1->GCR0 = 1U; // Bring the Module Out of Reset // stop the device for configuration sciREG1->GCR1 &= ~(1 << 7); // disable all interupts!!!! sciREG1->CLRINT = 0xFFFFFFFF; sciREG1->CLRINTLVL = 0xFFFFFFFF; // setup the UART for the LCD -> 1 start, 1 stop, no parity sciREG1->GCR1 = 0x0200002A; // Enable ONLY Transmit functionality! sciREG1->BAUD = 600; // baud rate --- 9600 from 80MHz VCLK sciREG1->LENGTH = 7; // 8 bit Data length sciREG1->FUN = 0x00000006; // Enabling Tx and Rx pins sciREG1->PSL = 0x00000006; //Enable PULL Up functionality for RX and TX Pins // clear flags sciREG1->FLR = 0xFFFFFFFF; // set bit 4, start the device sciREG1->GCR1 |= 0x00000080; //End of Module Configuration } void XX_LCD(void) { static uint8 u8blink = 0; uint8 i; uint16 u16waitCnt; // set cursor pos 4, set a . uint8 u8data[3] = {0xFE, 0x83, '.'}; // switch the blinking . every other second if (u8blink == 0) { u8blink = 1; u8data[2] = ' '; } else { u8blink = 0; } // write the 3 char buffer // TX 1st byte sciREG1->TD = u8data[0]; for (i=1; i< 3; i++) { u16waitCnt = 0; // wait for the SCI tx to become ready - SCIFLR / bit 8 TXRDY while ( ((sciREG1->FLR & SCI_TX_INT) == 0) || (u16waitCnt < 0x1500) ) // <---- Original code without this busy wait condition (counter)!! { u16waitCnt++; } sciREG1->TD = u8data[i]; } }