CCS/TM4C1299KCZAD: SRAM connection by EPI HB16 mode, can support up to 8pcs SRAM?

Hi Chia-Hung,

 The EPI0S24(BSEL0n)&EPI0S25(BSEL1n) acts byte select signals. When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data can be read and written at any address. The question to ask is if you will set the BSEL=1 or 0? Will you ever to a byte write to your memory bank? If you will want to perform byte writes to your memory banks then you might want to consider qualifying the WE input to the lower SRAM with the BSEL0n and qualifying the WE input to the upper SRAM with the BSEL1n.

 In the datasheet there is below note to consider when you set the BSEL=0.

When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes

at even addresses write invalid values into the odd byte. As a result, accesses should be made as

half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long

int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte

boundaries, the available address space is doubled. For example, 28 bits of address accesses 512

MB in this mode. Table 11-7 on page 829 shows the capabilities of the HB8 and HB16 modes as

well as the available address bits with the possible combinations of these bits.