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TMS570LS1224: TMS320F28379(Master)<->TMS570LS1224-MibSpi3(Slave)

Varun Malladi
Intellectual 270 points
Part Number: TMS570LS1224
Other Parts Discussed in Thread: HALCOGEN

Hello there,

I have trouble understanding how Mibspi3 works. The Master is sending an array of length 8.TG1_TX_DATA[8]. The code is already set as trigger always with no external source. Can you please tell me what are the basic steps I have to do to see the  array in Recieve buffer of TMS570? 

The master is sending Clock, MOSI, and CS pin. (TMS320 signals are perfect).

Although I tried with trigger always no external source, I do not understand when I am receiving data and even if I receive it most of the time it is wrong( shifted here and there), sometimes I get the correct data.

What's the use of TCKNT when there is no trigger?  How to use a trigger ?

I have a CS signal, should I use it for trigger and also should I give it to MIBSPICS[1] pin? (there is no MIBSPICS[0] on the launchpad).

I am really confused, what are the basic steps to see the correct data, help would be really appreciated. 

I have taken the basic Halcogen as reference. 

Thanks in advance!

Regards

Varun

  • 0
    Intellectual 270 points
    Are the spi3 pins same as Mibspi3?
  • 0 in reply to Varun Malladi
    TI__Guru**** 196346 points
    Hello Varun,

    1. You can configure MibSPI3/SPI3 module to run in compatibility mode or in multi-buffer mode. Both SPI3 and MibSPI3 use the same pins: CLK, CS, ENA, SOMI, SIMO

    2. In MibSPI slave mode, only CS0 and Transfer Group 0 can be used to TX/RX data. In slave mode, the fields like trigger source and trigger event are not taken into account by the sequencer. Only the CS pin (CS0) can trigger a Transfer Group (TG0).

    3. I posted an example (MibSPI1 (master)-->MibSPI3 (slave)) before, will search for you later.
  • 0 in reply to QJ Wang
    TI__Guru**** 196346 points
    Hello Varun,

    Here is the example CCS project:

    1. Master: MibSPI1, CS0, SOMI, SIMO, CLK. TG0 is used, 4 buffer; DMA is enabled to tx data from SRAM to MibSPI1 RAM TG0 buffer
    2. Slave: MibSPI3, CS0, SOMI, SIMO,CLK. TG0 is used, 4 buffer; DMA is enabled to tx data from MibSPI3 RAM TG0 buffer to SRAM

    e2e.ti.com/.../2552103
  • 0 in reply to QJ Wang
    Intellectual 270 points

    HI Wang,

    Thank you for your replies. I do no understand when you say "only the CS[0] pin can trigger a TG0. I do not have a MIBSPI3CS[0] pin on my 1224-launchpad. I have MibSPiNCS[1], MibSPiNCS[2],MibSPiNCS[3].

    I am kind of confused to which pin the CS from Master goes to trigger TG0. In the example you have enabled the MibSpi3 for receiving data and after enabling Mibspi1 you automatically send and receive the data, right?

    Regards

    Varun

  • 0 in reply to Varun Malladi
    TI__Guru**** 196346 points
    Hi Varun,

    In master side, you can use any CS pin and any transfer group to transmit data. In salve side, my test shows that only CS0 and TG0 can receive data (other CS doesn't work).

    In the example, MibSPI1 transmits data by enabling the TGENA in TGCTL register:
    mibspi->TGCTRL[group] |= 0x80000000U;

    In slave side, CS0 (active low) is the trigger.
  • 0 in reply to QJ Wang
    Intellectual 270 points
    Hi Wang,
    My Launchpad does not have Mibspi3NCS[0] pin. But Mibspi1 has Mibspi1NCS[0] at pin 58 on J9 port. And there are no pins connected to J6,7,8,9. Should I get a booster pack? If so can you suggest one?

    Regards
    Varun
  • 0 in reply to Varun Malladi
    TI__Guru**** 196346 points
    Hi Varun,

    If you use the Launchpad for LS12x, the MibSPI3CS_0 is the pin 5 of J6 header.