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SPI Interrupts in Multi-Buffer Mode

Evgenyy
Intellectual 490 points

Hi, everybody.

I need to generate SPI recieve interrupt when SPI RXRAM is full of new data. This situation is not clearly described in the TRM (spnu489a).

As I have understood from the TRM: "The RXOVRN interrupt is generated when a buffer in the RXRAM is overwritten by a new received word."

But I need to prevent such event (RX overrun) by reading RXRAM contents in RX interrupt. Though it is said that RX and TX interrupts are not used in Multi-Buffer mode.

Should I'd rather use "TG completed" or "TG suspended" interrupts for my purposes, and how to set up them correctly? There is an insufficient information about it in TRM.

In advance thanks, Evgenyy.

  • 0
    Intellectual 490 points

    I also unable to get Slave mode functionality of SPI module. I have 2 TMS570 USB sticks, one configured as SPI Master, and the other one as SPI Slave. I checked that MASTER and CLKMODE bits in GCR1 are both '1' for Master mode, and '0' for Slave mode. USB sticks are connected together and I can observe the transfer data and clocks on the oscilloscope, but when I try to read RXRAM on the slave SPI device, I get only zeros. TG is set as "Trigger Event = TGR_ALWAYS" and "Trigger Source = TRG_DISABLED", also "Buffer Mode = 4". I use Oneshot Transfer mode, and no Lock Transmittion, and no Chip Select Hold. I have tried to change SIMO, SOMI, CLK pin directions of the slave SPI, but the problem is still the same.

    Please, give me any suggestions.

  • 0 in reply to Evgenyy
    TI__Genius 13810 points

    Evgenyy,

    If you use TGR_ALWAYS, whenever you enable the transfer group in the master, a transfer will start. However, in order to make your slave device to response, you must enable the slave transfer group before you enable the master transfer group. Did you do that? [bit 31, offset /* 0x98  - 0xD4 */]

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Intellectual 490 points

    Yes, I set bit 31 in TGCTRL[0] register by spiTransfer(spiREG1, TGGR0) function (in my case: TGGR0 = 0), as I use "Transfer Group 0" for SPI Master and SPI Slave. The value in TGCTRL[0] = 0x40700000 for Master device and TGCTRL[0] = 0xC0700000 for Slave device, also SPIFLG = 0x0000300 for Master and SPIFLG = 0x0000200 for Slave. Still got the same...

     

  • 0 in reply to Evgenyy
    TI__Genius 13810 points

    Is that possible to send the code to me? I can take a look.

    My email: haixiao.weng@ti.com

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Intellectual 490 points

    Ok, have send you the code..

  • 0 in reply to Evgenyy
    TI__Genius 13810 points

    In your program:

        /* SPI1 set all pins to functional */
        spiREG1->PCFUN  =  1        /* SCS[0] */
     
                        | (1 << 2)  /* SCS[2] */
                        | (1 << 3)  /* SCS[3] */
                        | (1 << 8)  /* ENA */
                        | (1 << 9)  /* CLK */
                        | (1 << 10)  /* SIMO */
                        | (1 << 11); /* SOMI */
    1. In the master mode, that is fine. It means you might use all 4 CS pins. In the code, looks like the Master mode chooses CS_0 (you write 0xFE to TX RAM CS field). Here, I think you should change ENA to 0: 0<<8 since you didn’t use ENA pin.

        spiREG1->PCFUN  =  1        /* SCS[0] */
                        | (1 << 1)  /* SCS[1] */
                        | (1 << 2)  /* SCS[2] */
                        | (1 << 3)  /* SCS[3] */
                        | (0 << 8)  /* ENA */
                        | (1 << 9)  /* CLK */
                        | (1 << 10)  /* SIMO */
                        | (1 << 11); /* SOMI */

    2. In the slave mode, that is bad. It means you can only start transfer once all 4 CS pins are low. I think you should only select one CS pin (e.g CS0).
        spiREG1->PCFUN  =  1        /* SCS[0] */
                        | (0 << 1)  /* SCS[1] */
                        | (0 << 2)  /* SCS[2] */
                        | (0 << 3)  /* SCS[3] */
                        | (0 << 8)  /* ENA */
                        | (1 << 9)  /* CLK */
                        | (1 << 10)  /* SIMO */
                        | (1 << 11); /* SOMI */
    3. Then, you should connect two CS0 together (4 pin mode). And please release the SPISLAVE before you run the code in SPI master.

    4. Usually, when I initialize the slave ram, I put zeros in the CS field (bit 16-23 of TX RAM).

    Good Luck,

    Haixiao

  • 0 in reply to Haixiao Weng
    Intellectual 490 points

    It really works! Much more simple than a thought.

    Thanks a lot, Haixiao.