RM57L843: Why do you have to configure the R5-MPU-PMU the way it is written in the post?

Hello Zsolt,

The MPU on RM57 works with the L1 memory system (cache) to control accesses to and from L1 and external memory. The MPU enables you to partition memory into regions and set individual protection attributes for each region. The MPU on RM57 device supports 16 memory regions. Each region is programmed with a base address and size, and the regions can be overlapped to enable efficient programming of the memory map.

Each region has a number of attributes associated with it. These control how a memory access is performed when the processor accesses an address that falls within a given region. The attributes are:
• Memory type, one of:
— Strongly Ordered
— Device
— Normal
• Shared or Non-shared
• Non-cacheable
• Write-through Cacheable
• Write-back Cacheable
• Read allocation
• Write allocation

Each region can be given no access, read-only access, or read/write access permissions for Privileged or all modes. For example, if a User mode application attempts to access a Privileged mode access only region a permission fault occurs.

Please refer to ARM Architecture Reference Manual for details.