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CCS/RM48L952: Force N2HET1[18] High during Download & Debug

Jamie Wardlaw
Expert 1895 points
Part Number: RM48L952

Tool/software: Code Composer Studio

We have an external watchdog implementation that requires us to hold the WD_EN input high during download otherwise our watchdog trips due to lack of a pulse resulting in the inevitable download failure.

Is there any way, using a target configuration file, GEL file or similar; to force a specific GPIO to the high state during JTAG access - this would disable our watchdog and permit download. Other options we may have to explore are programming fixtures that probe this input holding it high but that is not something we want to commit to just now, if we can find a solution through configuration of JTAG sessions.

Thanks

JW

  • 0
    TI__Mastermind 49120 points
    Hi Jamie,

    CCS ships with default gel files for each MCU. The relevant gel file gets automatically included when you create a new project and define the target MCU. You can find the gel files under the "C:\ti\ccsv8\ccs_base\emulation\gel" folder typically.

    The gel files define functions and "menuitem"s that become executable commands from under the Gel menu item in CCS. The rm48l952.gel file has a function to swap flash and RAM memory addresses for example.

    You can create your own function to set the N2HET1[18] pin High before you download the updated program. The minimum number of registers required to set this pin High are: CLKCNTL.PENA (to release peripherals from reset), PSPWRDWNCLR0.17 (to enable clock to the N2HETx modules), and then to the N2HET1 registers to drive this pin High as a GPIO.

    Note that the JTAG would have to connect to the part first and then execute this GEL command. There may be a race between you being able to execute the GEL command to drive this pin High and the external watchdog resetting tripping.

    Let me know how it goes.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Expert 1895 points

    Thanks Sunil,

    I did consider the race condition and think it will become a blocker on this approach. But regardless, i'm interested to see how to use GEL to control the MCU peripherals during debug.

    i've added the following  defines and pointers to necessary registers

    #define HETREG1_DIRBASE     0xFFF7B84C
#define HETREG1_DOUTBASE    0xFFF7B854
#define HETREG1_DSETBASE    0xFFF7B858
#define HETPORT1_BASE       0xFFF7B84C
#define CLKCNTL_BASE        0xFFFFFFD0
#define PSPWRDWNCLR0_BASE   0xFFFFE0A0   

unsigned int *clkcntl = (unsigned int *) CLKCNTL_BASE;
unsigned int *pspwrdwnclr0 = (unsigned int *) PSPWRDWNCLR0_BASE;
unsigned int *hetreg1dir = (unsigned int *) HETREG1_DIRBASE;
unsigned int *hetreg1dout = (unsigned int *) HETREG1_DOUTBASE;
unsigned int *hetreg1dset = (unsigned int *) HETREG1_DSETBASE;

    And in OnTarget connext i've added the following:

        /* Clock Enable */
    *clkcntl |= 0x00000100U;

    /* Enable clocks to Peripherals */
    *pspwrdwnclr0 = 0xFFFFFFFFU;

    
    /* Set HET1 default output values & direction */
    *hetreg1dout =          (uint32)((uint32)1U << 18U);

    I intended to then set hetreg1dir & hetreg1dset appropriately but I cannot get the debugger to successfully connect if I try to set hetreg1dout. Commenting out this line and just setting clkcntl and pspwrdwnclr0 seems to be OK. Do I have to do something else before messing with the het1 memory?

    I have basically tried to just replicate het_init and the logic of gioSetBit but everytime CCS crashes.

    some example code for setting one het1 channel to ON would be much appreciated.

    Thanks

    Jamie

  • 0 in reply to Jamie Wardlaw
    Expert 1895 points
    Update... the code above that was setting the het1 registers was using the unknown type uint32. I've explicitly typed with 'unsigned int' and I no longer get crashes. I now see nhet activity during JTAG connect so will try to verify the timings and how we interact on the watchdog.
  • 0 in reply to Jamie Wardlaw
    Expert 1895 points 
    /*                                                                            */
/* Author : JWardlaw July 19th 2018                                           */
/*                                                                            */
/*                                                                            */
/* File:            csi_rm48L952_wdog_dis.gel                                 */
/*                                                                            */
/* Note: This GEL file is provided as an example and might be used for        */
/*       software development for the RM48L952 microcontroller. Before        */
/*       usage it is recommended to check if the file provides the            */
/*       functionality expected.                                              */
/*                                                                            */
/*                                                                            */

/*----------------------------------------------------------------------------*/
/* Definitions - Memory Map Specifiers                                        */
#define FLASH   0
#define RAM     1
#define nEMIF   0
#define EMIF    1

/*----------------------------------------------------------------------------*/
/* Definitions - Text Format Specifiers                                       */
#define BLACK   0
#define BLUE    1
#define RED     2 

/*----------------------------------------------------------------------------*/
/* Definitions - Memory Switch                                                */
#define STARTED 0
#define COMPL   1

/*----------------------------------------------------------------------------*/
/* Global Variables - Default Memory Map                                      */
unsigned int MemoryMap  = FLASH;

/*----------------------------------------------------------------------------*/
/* Global Variables - Memory Switch                                           */
unsigned int MemSwitchState = COMPL;


/*----------------------------------------------------------------------------*/
/* HET Control during JTAG Access */                                             

#define HETREG1_DIRBASE     0xFFF7B84C
#define HETREG1_DOUTBASE    0xFFF7B854
#define HETREG1_DSETBASE    0xFFF7B858
#define HETREG1_GCRBASE     0xFFF7B800
#define HETPORT1_BASE       0xFFF7B84C
#define CLKCNTL_BASE        0xFFFFFFD0
#define PSPWRDWNCLR0_BASE   0xFFFFE0A0   

unsigned int *clkcntl = (unsigned int *) CLKCNTL_BASE;
unsigned int *pspwrdwnclr0 = (unsigned int *) PSPWRDWNCLR0_BASE;
unsigned int *hetreg1gcr = (unsigned int *) HETREG1_GCRBASE;
unsigned int *hetreg1dir = (unsigned int *) HETREG1_DIRBASE;
unsigned int *hetreg1dout = (unsigned int *) HETREG1_DOUTBASE;
unsigned int *hetreg1dset = (unsigned int *) HETREG1_DSETBASE;

/*----------------------------------------------------------------------------*/
/* Function - StartUp()                                                       */
/*                                                                            */
StartUp(){

} /* StartUp() */

/*----------------------------------------------------------------------------*/
/* Function - OnResetDetected()                                               */
/*                                                                            */
OnResetDetected(){

    if(MemSwitchState == COMPL){
    
        memmap(FLASH, EMIF);
        MemoryMap = FLASH;
        GEL_TextOut("\tMemory Map Setup for Flash @ Address 0x0 due to System Reset\n",,,,,);
    }
    
    if(MemSwitchState == STARTED)
     
        MemSwitchState == COMPL;
    }
/*----------------------------------------------------------------------------*/
/* Function - OnTargetConnect()                                               */
/*                                                                            */
OnTargetConnect(){

    if(MemoryMap == FLASH){
        memmap(FLASH, EMIF);
        GEL_TextOut("\tMemory Map Setup for Flash @ Address 0x0",,,,,);
    }    
    if(MemoryMap == RAM){
        memmap(RAM, EMIF);
        GEL_TextOut("\tMemory Map Setup for RAM @ Address 0x0.",,,,,);
        GEL_TextOut("\tFor Debugging Only!",,,,,);
    }

    /* Disable Watchdog */
    GEL_TextOut("\n[CSI] Disabling Watchdog\n",,,,,);
    /* Clock Enable */
    *clkcntl |= 0x00000100U;
    GEL_TextOut("\n[CSI] Clock Enabled\n",,,,,);
    /* Enable clocks to Peripherals */
    *pspwrdwnclr0 = 0xFFFFFFFFU;
    GEL_TextOut("\n[CSI] Peripherals Clock Enabled\n",,,,,);
    
    /* Set HET1 default output values & direction */
    *hetreg1dout =          (unsigned int)((unsigned int)0U << 31U)
                          | (unsigned int)((unsigned int)0U << 30U)
                          | (unsigned int)((unsigned int)0U << 29U)
                          | (unsigned int)((unsigned int)0U << 28U)
                          | (unsigned int)((unsigned int)0U << 27U)
                          | (unsigned int)((unsigned int)0U << 26U)
                          | (unsigned int)((unsigned int)0U << 25U)
                          | (unsigned int)((unsigned int)0U << 24U)
                          | (unsigned int)((unsigned int)0U << 23U)
                          | (unsigned int)((unsigned int)0U << 22U)
                          | (unsigned int)((unsigned int)0U << 21U)
                          | (unsigned int)((unsigned int)0U << 20U)
                          | (unsigned int)((unsigned int)0U << 19U)
                          | (unsigned int)((unsigned int)1U << 18U)
                          | (unsigned int)((unsigned int)0U << 17U)
                          | (unsigned int)((unsigned int)0U << 16U)
                          | (unsigned int)((unsigned int)0U << 15U)
                          | (unsigned int)((unsigned int)0U << 14U)
                          | (unsigned int)((unsigned int)0U << 13U)
                          | (unsigned int)((unsigned int)0U << 12U)
                          | (unsigned int)((unsigned int)0U << 11U)
                          | (unsigned int)((unsigned int)0U << 10U)
                          | (unsigned int)((unsigned int)0U << 9U)
                          | (unsigned int)((unsigned int)0U << 8U)
                          | (unsigned int)((unsigned int)0U << 7U)
                          | (unsigned int)((unsigned int)0U << 6U)
                          | (unsigned int)((unsigned int)0U << 5U)
                          | (unsigned int)((unsigned int)0U << 4U)
                          | (unsigned int)((unsigned int)0U << 3U)
                          | (unsigned int)((unsigned int)0U << 2U)
                          | (unsigned int)((unsigned int)0U << 1U)
                          | (unsigned int)((unsigned int)0U << 0U);
    
    GEL_TextOut("\n[CSI] HET1 defaults set\n",,,,,);
    
    *hetreg1dir =           (unsigned int) 0x00000000U
                            | (unsigned int) 0x40000000U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x10000000U
                            | (unsigned int) 0x08000000U
                            | (unsigned int) 0x04000000U
                            | (unsigned int) 0x02000000U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x00400000U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x00100000U
                            | (unsigned int) 0x00080000U
                            | (unsigned int) 0x00040000U
                            | (unsigned int) 0x00020000U
                            | (unsigned int) 0x00010000U
                            | (unsigned int) 0x00008000U
                            | (unsigned int) 0x00004000U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x00001000U
                            | (unsigned int) 0x00000800U
                            | (unsigned int) 0x00000400U
                            | (unsigned int) 0x00000200U
                            | (unsigned int) 0x00000100U
                            | (unsigned int) 0x00000080U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x00000000U
                            | (unsigned int) 0x00000010U
                            | (unsigned int) 0x00000008U
                            | (unsigned int) 0x00000004U
                            | (unsigned int) 0x00000002U
                            | (unsigned int) 0x00000001U;
    GEL_TextOut("\n[CSI] HET1 direction set",,,,,);

    *hetreg1gcr = ( 0x00000001U 
                        | (unsigned int)((unsigned int)0U << 24U)
                        | (unsigned int)((unsigned int)1U << 16U)
                        | (0x00020000U));
        
    GEL_TextOut("\n[CSI] HET1 GCR set\n",,,,,);
    
} /* OnTargetConnect() */

/*----------------------------------------------------------------------------*/
/* Function - memmap(memSel, extMem)                                          */
/*                                                                            */
memmap(memSel, extMem){

    GEL_MapOff();
    GEL_MapReset(); 

    /* Flash / RAM Definition */
    if(memSel == FLASH){

        /* Flash Definition */
        GEL_MapAdd(0x00000000, 0, 0x00300000, 1, 0); /* Internal Flash ()     */
        GEL_MapAddStr(0xF0400000, 0, 0x00060000, "R|AS2", 0); /* Internal Flash ECC    */        
        GEL_MapAdd(0x08000000, 0, 0x00040000, 1, 1); /* Internal RAM          */
        GEL_MapAdd(0x08400000, 0, 0x00040000, 1, 1); /* Internal RAM ECC      */
        GEL_MapAdd(0x20000000, 0, 0x00300000, 1, 0); /* Mirrored Flash        */        
        GEL_MapAdd(0xFE000000, 0, 0x01000000, 1, 1); /* CRC/PSA               */
    }

    if(memSel == RAM){

        /* RAM Definition */
        GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal RAM          */
        GEL_MapAdd(0x00400000, 0, 0x00040000, 1, 1); /* Internal RAM ECC      */
        GEL_MapAdd(0x08000000, 0, 0x00300000, 1, 0); /* Internal Flash ()     */
        GEL_MapAddStr(0xF0400000, 0, 0x00060000, "R|AS2", 0); /* Internal Flash ECC    */        
        GEL_MapAdd(0x20000000, 0, 0x00300000, 1, 0); /* Mirrored Flash        */        
        GEL_MapAdd(0xFE000000, 0, 0x01000000, 1, 1); /* CRC/PSA               */
    }

    if(extMem == EMIF){

        GEL_MapAdd(0x60000000, 0, 0x10000000, 1, 1); /* External Async Memory       */
        GEL_MapAdd(0x80000000, 0, 0x08000000, 1, 1); /* External Sync SDRAM Memory       */
    }

    /* Other Flash Related Memories*/
    GEL_MapAdd(0xF0200000, 0, 0x00010000, 1, 0); /* EEPROM                    */
    GEL_MapAddStr(0xF0100000, 0, 0x00002000, "R|AS2", 0); /* EEPROM ECC               */
    GEL_MapAdd(0xF0000000, 0, 0x00004000, 1, 0); /* Customer OTP                      */
    GEL_MapAddStr(0xF0040000, 0, 0x00000800, "R|AS2", 0); /* Customer OTP ECC         */
    GEL_MapAdd(0xF000E000, 0, 0x00001000, 1, 0); /* Customer OTP, EEPROM              */
    GEL_MapAddStr(0xF0041C00, 0, 0x00000400, "R|AS2", 0); /* Customer OTP, EEPROM ECC         */

    
    /* Peripheral Register Definition */
    GEL_MapAdd(0xFFF7FC00, 0, 0x00000200, 1, 1); /* SPI5       - PS00         */
    GEL_MapAdd(0xFFF7FA00, 0, 0x00000200, 1, 1); /* SPI4       - PS01         */
    GEL_MapAdd(0xFFF7F800, 0, 0x00000200, 1, 1); /* SPI3       - PS01         */
    GEL_MapAdd(0xFFF7F600, 0, 0x00000200, 1, 1); /* SPI2       - PS02         */
    GEL_MapAdd(0xFFF7F400, 0, 0x00000200, 1, 1); /* MIBSPI1    - PS02         */
    GEL_MapAdd(0xFFF7E400, 0, 0x00000100, 1, 1); /* LIN        - PS06         */
    GEL_MapAdd(0xFFF7E500, 0, 0x00000100, 1, 1); /* SCI        - PS06         */
    GEL_MapAdd(0xFFF7E000, 0, 0x00000200, 1, 1); /* DCAN3      - PS07         */
    GEL_MapAdd(0xFFF7DE00, 0, 0x00000200, 1, 1); /* DCAN2      - PS08         */
    GEL_MapAdd(0xFFF7DC00, 0, 0x00000200, 1, 1); /* DCAN1      - PS08         */
    GEL_MapAdd(0xFFF7D400, 0, 0x00000100, 1, 1); /* I2C        - PS10         */
    GEL_MapAdd(0xFFF7C200, 0, 0x00000200, 1, 1); /* MIBADC2    - PS15         */
    GEL_MapAdd(0xFFF7C000, 0, 0x00000200, 1, 1); /* MIBADC1    - PS15         */
    GEL_MapAdd(0xFFF7BC00, 0, 0x00000100, 1, 1); /* GIO        - PS16         */
    GEL_MapAdd(0xFFF7B800, 0, 0x00000100, 1, 1); /* NHET1      - PS17         */
    GEL_MapAdd(0xFFF7B900, 0, 0x00000100, 1, 1); /* NHET2      - PS17         */
    GEL_MapAdd(0xFFF7A400, 0, 0x00000100, 1, 1); /* HET TU     - PS22         */
    GEL_MapAdd(0xFFF7A500, 0, 0x00000100, 1, 1); /* HET TU2     - PS22         */

    
    /* Peripheral Memory */
    GEL_MapAdd(0xFC520000, 0, 0x00002000, 1, 1); /* CPPI, Ethernet RAM - PS05 */
    GEL_MapAdd(0xFF0A0000, 0, 0x00020000, 1, 1); /* MibSPI5 RAM    - PS05     */
    GEL_MapAdd(0xFF0C0000, 0, 0x00020000, 1, 1); /* MibSPI3 RAM    - PS06     */
    GEL_MapAdd(0xFF0E0000, 0, 0x00020000, 1, 1); /* MibSPI1 RAM    - PS07     */
    GEL_MapAdd(0xFF1A0000, 0, 0x00020000, 1, 1); /* CAN3 RAM       - PS13     */
    GEL_MapAdd(0xFF1C0000, 0, 0x00020000, 1, 1); /* CAN2 RAM       - PS14     */
    GEL_MapAdd(0xFF1E0000, 0, 0x00020000, 1, 1); /* CAN1 RAM       - PS15     */
    GEL_MapAdd(0xFF3A0000, 0, 0x00020000, 1, 1); /* MIBADC2 RAM    - PS29     */
    GEL_MapAdd(0xFF3E0000, 0, 0x00020000, 1, 1); /* MIBADC1 RAM    - PS31     */
    GEL_MapAdd(0xFF440000, 0, 0x00020000, 1, 1); /* NHET2 RAM       - PS34     */
    GEL_MapAdd(0xFF460000, 0, 0x00020000, 1, 1); /* NHET1 RAM       - PS35     */
    GEL_MapAdd(0xFF4C0000, 0, 0x00020000, 1, 1); /* HET2 TU RAM     - PS38     */
    GEL_MapAdd(0xFF4E0000, 0, 0x00020000, 1, 1); /* HET1 TU RAM     - PS39     */

    /* System Peripheral Register */
    GEL_MapAdd(0xFE000000, 0, 0x01000000, 1, 1); /* CRC                       */
    GEL_MapAdd(0xFFA00000, 0, 0x00001000, 1, 1); /* CoreSight Debug ROM       */
    GEL_MapAdd(0xFFA01000, 0, 0x00001000, 1, 1); /* R4 Debug Register         */
    GEL_MapAdd(0xFFA02000, 0, 0x00001000, 1, 1); /* ETM-R4 Register           */
    GEL_MapAdd(0xFFA03000, 0, 0x00001000, 1, 1); /* CoreSight TPIU Register   */
    GEL_MapAdd(0xFFA04000, 0, 0x00001000, 1, 1); /* POM Register              */
    GEL_MapAdd(0xFFF80000, 0, 0x00001000, 1, 1); /* DMA RAM                   */
    GEL_MapAdd(0xFFF82000, 0, 0x00001000, 1, 1); /* VIM RAM                   */
    GEL_MapAdd(0xFFF83000, 0, 0x00001000, 1, 1); /* RTP RAM                   */
    GEL_MapAdd(0xFFF87000, 0, 0x00001000, 1, 1); /* Flash Wrapper Register    */
    GEL_MapAdd(0xFFF8C000, 0, 0x00001000, 1, 1); /* eFuse Farm Controller     */
    GEL_MapAdd(0xFFFF0000, 0, 0x00000200, 1, 1); /* Power Management Register */
    GEL_MapAdd(0xFFFFE000, 0, 0x00000100, 1, 1); /* PCR Register              */
    GEL_MapAdd(0xFFFFE100, 0, 0x00000100, 1, 1); /* System 2 Register         */
    GEL_MapAdd(0xFFFFE400, 0, 0x00000200, 1, 1); /* PBIST                     */
    GEL_MapAdd(0xFFFFE600, 0, 0x00000100, 1, 1); /* STC                       */    
    GEL_MapAdd(0xFFFFEA00, 0, 0x00000200, 1, 1); /* IOMM                      */    
    GEL_MapAdd(0xFFFFEC00, 0, 0x00000100, 1, 1); /* DCC1                      */    
    GEL_MapAdd(0xFFFFF000, 0, 0x00000400, 1, 1); /* DMA                       */
    GEL_MapAdd(0xFFFFF400, 0, 0x00000100, 1, 1); /* DCC2                       */    
    GEL_MapAdd(0xFFFFF500, 0, 0x00000100, 1, 1); /* ESM                       */
    GEL_MapAdd(0xFFFFF600, 0, 0x00000100, 1, 1); /* CCMR4                     */
    GEL_MapAdd(0xFFFFF700, 0, 0x00000100, 1, 1); /* DMM                       */
    GEL_MapAdd(0xFFFFF800, 0, 0x00000100, 1, 1); /* RAM ECC even              */
    GEL_MapAdd(0xFFFFF900, 0, 0x00000100, 1, 1); /* RAM ECC odd               */
    GEL_MapAdd(0xFFFFFA00, 0, 0x00000100, 1, 1); /* RTP                       */
    GEL_MapAdd(0xFFFFFC00, 0, 0x00000100, 1, 1); /* RTI Register              */
    GEL_MapAdd(0xFFFFFD00, 0, 0x00000100, 1, 1); /* VIM Parity                */
    GEL_MapAdd(0xFFFFFE00, 0, 0x00000100, 1, 1); /* VIM Register              */
    GEL_MapAdd(0xFFFFFF00, 0, 0x00000100, 1, 1); /* System Register           */
    
    /* EMIF/Ethernet Registers */
    GEL_MapAdd(0xFCFFE800, 0, 0x00000100, 1, 1); /* EMIF                      */
    GEL_MapAdd(0xFCF78000, 0, 0x00000400, 1, 1); /* CPGMAC Slave              */
    GEL_MapAdd(0xFCF78800, 0, 0x00000100, 1, 1); /* CPGMACSS Wrapper          */
    GEL_MapAdd(0xFCF78900, 0, 0x00000100, 1, 1); /* Ethernet MDIO             */
        GEL_MapAddStr(0xFCF78A00, 0, 0x00000080, "R|W|AS2", 1); /* W2FC USB Device           */
        GEL_MapAdd(0xFCF78B00, 0, 0x00000100, 1, 1); /* OHCI USB HOST           */
    
    GEL_MapOn();

} /* Function - memmap(memSel, extMem) */

/*----------------------------------------------------------------------------*/
/* Function - swap_mem(memSel)                                                */
/*                                                                            */
swap_mem(memSel){
    
    GEL_TextOut("NOTES:\n\tThe Flash/RAM memory adresses of the device will be switched.");
    GEL_TextOut("\tAt the end of this routine the device will be reset.");
    GEL_TextOut("\tThis might lead to an popup message stating an error!");
    GEL_TextOut("\tJust re-connect after the message appeared.");

    MemSwitchState = STARTED;
    
    if(memSel == RAM){

        memmap(RAM, EMIF);
        MemoryMap = RAM;
        *(int *) 0xffffffc4 = 0x05050505;
        *(int *) 0xffffffcc = 0x00000001;
        *(int *) 0xffffffcc = 0x00000000;
    }

    if(memSel == FLASH){

        memmap(FLASH, EMIF);
        MemoryMap = FLASH;
        *(int *) 0xffffffc4 = 0x0A0A0A0A;
        *(int *) 0xffffffcc = 0x00000001;
        *(int *) 0xffffffcc = 0x00000000;
    }
    
    MemSwitchState = COMPL;
    
    GEL_TextOut("\tMemory swap is done.");
    GEL_TextOut("\tIn case a popup message appaered, re-connect to the device.");
    
    
} /* swap_mem(memSel) */

/*----------------------------------------------------------------------------*/
/* MenuItem - "RM48L952 Memory Map Setup"                                */
/*                                                                            */
menuitem "RM48L952 Memory Map Setup";

    hotmenu CCS_MemMap_FLASH_at_0x0(){

        memmap(FLASH, EMIF);
        GEL_TextOut("\tMemory Map Setup for Flash @ Address 0x0",,,,,);
        
    }

    hotmenu CCS_MemMap_RAM_at_0x0(){
    
        memmap(RAM, EMIF);
        GEL_TextOut("\tMemory Map Setup for RAM @ Address 0x0.",,,,,);
        GEL_TextOut("\tFor Debugging Only!",,,,,);

    }

/*----------------------------------------------------------------------------*/
/* MenuItem - "RM48L952 Memory Switch"                                   */
/*                                                                            */
menuitem "RM48L952 Memory Switch";

    hotmenu Target_Flash_to_0x0(){

        swap_mem(FLASH);
    }

    hotmenu Target_RAM_to_0x0(){
    
        swap_mem(RAM);
    }

    I got this working. But the race conditions during a download will prevent it being a viable solution. As the MCU is in an unkwnon state during download our signal to our watchdog IC is typically low meaning the watchdog is ON. After 1 sec, with no pulse, the reset is commanded which of course kills our program load. For reference, here is the GEL file I got working to successfully toggle the NHET pin on a regular connection to the target.

  • 0 in reply to Jamie Wardlaw
    TI__Mastermind 49120 points
    Jamie,

    You don't need to write to the HETGCR0 register to turn the HET ON. That is the control for the HET processing engine to start executing the HET program. You can leave the HET off to just be able to drive the N2HET1[18] pin High as GPIO.