Other Parts Discussed in Thread: TMS570LC4357
Tiva-C (at least some models) have support for using external SDRAM and/or Flash. It's possible to run code from SDRAM and Flash. Fine, that much is clear.
Now the devil is in the details, being able to run code and reasonably doing so are two different things. As far as I can tell, Tiva does not have any kind of caching going on. If instructions are fetched one-by-one from the SDRAM, it's not exactly efficient process. Is the memory controller smart enough to at least combine two word reads for a single long instruction into one transaction? If we use typical 16-bit SDRAM as an example, at 60MHz clock it'd work out like so:
Alliance AS4C4M16SA 143MHz part would work out with 60MHz clock to tRCD = 2 clk, CAS = 2clk, tRAS = 3clk, tRP=2clk
- So if we do this in the most un-optimal way possible, it'd be tRAS + tRP 3+2 = 5 cycles for each word.. Hardly optimal at 83ns / pop. To make things even worse, you need two words so it'd be 10 clocks or 167ns for two accesses or 6MHz instruction clock!
- It's possible to do multiple reads at one time so grabbing two words for one instruction back to back, it'd be slightly less painful at 6 clocks or 10MHz instruction clock. .
- Ideally the SDRAM controller "knows" about rows and doesn't deselect the device in-between accesses, you'd be looking at 3 clocks per long or 20MHz instruction clock.
So which option are you dealing with when using SDRAM for running code?
