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Hi,
I had a conceptual question: Using the SPNU501H doc and chapter 5 recommended flows for write and erase, I can see that on the write side usage of Fapi_issueProgrammingCommand() allows the use of a mode argument to make sure ECC is auto generated.
Could you confirm that the same is true for the usage of Fapi_issueAsyncCommandWithAddress() for a sector or bank erase, that the ECC is autogenerated for the erased 0xFF's and written into the ECC range, so that the ESM is happy? i think this is the case. Does the Fapi_enableAutoEccCalculation() need to be enabled for this?
Thanks,
--Gunter
On this R5 based device, ECC is enabled by default. Programming and erasing is done by a state machine and can be done on Flash memory without the ECC being programmed. The two issues that come up are memory holes at the end of cache line fills and trying to do blank checks. To avoid getting an ECC error when the cache controller grabs a line that is only partially full of data or code, in the link command file, use a fill for each section, or replace the "align(32)" with "palign(32)" so that ECC is generated for all 32 bytes in the cache line.
SECTIONS { /* USER CODE BEGIN (5) */ .intvecs : {} > VECTORS .text palign(32) : {} > FLASH0 | FLASH1 .const palign(32) : {} > FLASH0 | FLASH1 .cinit palign(32) : {} > FLASH0 | FLASH1 .pinit palign(32) : {} > FLASH0 | FLASH1 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM #if 0 /* USER CODE END */ .intvecs : {} > VECTORS .text align(32) : {} > FLASH0 | FLASH1 .const align(32) : {} > FLASH0 | FLASH1 .cinit align(32) : {} > FLASH0 | FLASH1 .pinit align(32) : {} > FLASH0 | FLASH1 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM /* USER CODE BEGIN (6) */ #endif
The flash API function for blank check uses a special test mode to verify that the data and ECC bits are all FF.