Customer trying to find root cause for a recent rise (1.6%) in production failures of their PCB design which uses a Micrel KSZ8041RNL PHY connected to a TI TM4C1292 processor via RMII. While in the failure mode the board gets Ethernet link but data is inconsistent and results in DHCP timeouts or sometimes no data at all. Replacing the PHY or the TM4C1292 restores proper functionality but the failure does not follow the chip if they solder it onto another known-good board. Heating the PHY or TM4C1292 makes a failed board work better and freezing makes it worse. In the failure mode, auto negotiation appears to fail in an endless loop.
This data seems to point to a timing issue between the two chips so they began experimenting with the timing of the RMII interface. In the design the PHY has a 25MHz crystal and it internally generates a 50MHz REFCLK that is then sent to the TM4C1292 MAC. Delaying the REFCLK that is sent to the TM4C1292 by a few nanoseconds causes a failed board to function properly (and at 100Mbps). They also tried forcing the link speed to 10Mbps which causes a failed board to operate properly, albeit slower.
A study of the datasheets revealed a possible timing violation that they would like TI to evaluate:
A) “Output Delay” on Page 49 of the PHY datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/ksz8041nl_rnl.pdf
B) RMII transmit and receive timing parameters on page 1807 of the TM4C1292 datasheet (particularly parameter N87).
