TM4C1294NCPDT: EPI Host Bus mode setup

Hi
The following code may help.

EPIModeSet(EPI0_BASE, EPI_MODE_HB16); //general mode EPI_MODE_GENERAL EPI_MODE_HB16
EPIDividerSet(EPI0_BASE, 10); //1=60MHz, 10=10MHz, 119=1MHz Sets the clock divider for the EPI module’s CS0n/CS1n.
EPIConfigHB16Set(EPI0_BASE,
EPI_HB16_MODE_ADDEMUX | //sets data and address muxed, AD[15:0].
EPI_HB16_WRWAIT_3 | //sets write wait state to 2 EPI clocks.
EPI_HB16_RDWAIT_3 | //sets read wait state to 2 EPI clocks.
EPI_HB16_CLOCK_GATE_IDLE| // holds the EPI clock low when no data is available to read or write.
EPI_HB16_CSCFG_CS, //sets address latch active low.
1); // the maximum number of external clocks to wait if a FIFO ready signal is
//holding off the transaction.

EPIAddressMapSet(EPI0_BASE,
EPI_ADDR_PER_SIZE_256MB | //256MB location
EPI_ADDR_PER_BASE_A); //EPI0 is mapped from 0xA0000000 to 0xA00000FF.

// Set the EPI memory pointer to the base of EPI memory space. Note that
// g_pui16EPISdram is declared as volatile so the compiler should not
// optimize reads out of the memory. With this pointer, the memory space
// is accessed like a simple array.
g_pui16EPISdram = (uint16_t *)0xA0000000;

// READ WRITE OPERARION FOR VERIFICATION
// A= g_pui16EPISdram[0];

Regards,
Digvijay