This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: Does it take a few cycles to temporarily disable the HET interrupt?

Part Number: TMS570LS3137

The quick question is -- does the statement "hetREG1->INTENAC = 1;" immediately suspend the HET interrupt or does it take a few cycles, and if it takes a few cycles, why?

In my application, I have the HET bound to the FIQ interrupt, and I have some shared-data between this FIQ interrupt and a separate IRQ interrupt, so I have the need to temporary suspend the HET interrupt in order to update the shared data. My data suggests that after the line-of-code "hetREG1->INTENAC = 1;", the interrupt can still occur within the next few lines of code. My solution is as follows:

hetREG1->INTENAC = 1;
INLINE_NOP();
INLINE_NOP();
INLINE_NOP();
return();

And this appears to work 100% of the time; do these 3 NOPs after disabling the HET interrupt make sense, and if so, why?

Thanks,

Jim

  • Jim,

    Writes to peripheral registers are buffered so that the CPU is not held while the write finishes. This is what you are observing.

    You can also add a loop to read back from the INTENA register until the bit is actually cleared.

    Regards,
    Sunil
  • Sunil,
    Thank you for the quick reply. Is the delay known to be less than a few (like 3) cycles? I need this code to be as fast as possible, so adding a while(reg-not-set) plus bounding because we don't want unbounded while loops would be a lot of overhead, and if it was known to be less than 3 or 4 cycles, I will just keep the few NOPs.
    Thanks,
    Jim
  • Jim,

    The delay to write to the register could be variable. One way to make sure that the write to the INTENA register completes is to read from this register after a write. Then you will not need any loop for this, just a single read. This does cause you to lose the advantage of the buffering on the write path, as now the read from the register will be "held" until the write completes.

    Regards,
    Sunil