There seem to be conditions when external un-configured analog VBUS, ID pins register control via USBGPCS can randomly change back to POR state in USBLIB control of them.
Does Tivaware USB library randomly check status of USBGPCS 0x41C to determine host connected end points are indeed still connected?
It would seem VBUS, ID pins being un-configured and forced HIGH via USBGPCS can arbitrarily revoke pins enable status if not being refreshed in some consistent time frame. Likewise GPIO enabled analog VBUS, ID pins seem to have less frequent client endpoint disconnects but they do randomly occur as well. It would seem USB0 clock control and register reads are not without pitfalls relative to other peripherals that occupy the AHB bus at the very same time.
Point is the AHB timing of USB0 and register reads of USBGPCS randomly exhibit evidence (errata) of skipping CPU ticks when several other NVIC interrupt sources (consistently) occupy the AHB. That is the most logical deduction that can be concluded in the erratic behavior of USB0 endpoints being randomly disconnected for no good reason. We happen to link high PWM peripheral active with NVIC and application execution (CPU) being highly suspect in AHB timing issues relative to USB library calls refreshing status from the bits being set in USBGPCS register.