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TMS570LC4357: STC / LBIST Maximum Clock Rate

ninja
Prodigy 250 points
Part Number: TMS570LC4357

The current documentation regarding LBIST / STC clock rate is unclear. I'd like to clarify the following points:

1) What is the maximum allowed clock rate for STC1 Segment 0 testing?

2) What effect does STCLKDIV.CLKDIV have on the input clock? Is it identical to STCCLKDIV.CLKDIV0 / STCCLKDIV.CLKDIV1? ("Division ratio will be n+1?")

    2a) Is there any meaningful difference between setting STCLKDIV.CLKDIV = n, vs setting STCLKDIV.CLKDIV = 0, STCCLKDIV.CLKDIV0 = n, STCCLKDIV.CLKDIV1 = n?

Thank you for the help.

  • 0
    TI__Mastermind 21425 points
    Hello ninja,
    1. Maximum clock for STC1 Segment 0 is 110 MHz;
    2. Division ratio in STCCLKDIV (@ 0xFFFF E644) will have effect only when the value in the CLKDIV field of the STCLKDIV register (@ 0xFFFF E108h) from SYS2 module is zero and this is done for software compatibility. Division ratio will be n+1 .
    2a) In case you use STCLKDIV.CLKDIV, same divider will be active for both segments. In case of using STCCLKDIV.CLKDIV0/1 division raion for each segment could be different.

    Best regards,
    Miro