CCS/TM4C129ENCPDT: TM4C129ENCPDT ISR from RAM

Lukasz Huchel

Part Number: TM4C129ENCPDT

Tool/software: Code Composer Studio

HI,

In my code the .intvecs memory section is linked to FLASH. There is no copying of the vector table to RAM during initialization. For example I do work also with MCUs from C2000 family where the memcpy((void *)0x000D00, &PieVectTableInit ....) is used to copy the interrupt vector table. In this case interrupt table is located in RAM so it has to be copied for proper operation, whereas, in case of TM4C129 table is located at the beginning of on-chip Flash memory 0x0000.0000.

Does TM4C129 support some optimized pre-fetch mechanism which allows for fast execution of interrupt routines from Flash? Datasheet mentions possibility of introducing offset to the vector table location, however, TivaWare examples (I look at enet_lwip in particular) do not use the offset option what means that ISR are fetched from flash memory.

/* Section allocation in memory */

SECTIONS
{
    .intvecs:   > APP_BASE
    .text   :   > FLASH
    .const  :   > FLASH
    .cinit  :   > FLASH
    .pinit  :   > FLASH
    .init_array : > FLASH

    .vtable :   > RAM_BASE
    .data   :   > SRAM
    .bss    :   > SRAM
    .sysmem :   > SRAM
    .stack  :   > SRAM
}

The vector table defined in startup_ccs.c is linked to .intvecs section:

#pragma DATA_SECTION(g_pfnVectors, ".intvecs")

I will appreciate insight of experienced users.


Thank you

over 7 years ago

0 Charles Tsai over 7 years ago

TI__Guru**** 191846 points

Hi Lukasz,

The vector table is relocatable. This is done by programming the VTABLE register in the M4 processor. Please refer to the datasheet for details. If you want to see how it is done, you can refer to the bl_startup_ccs.s file for the bootloader. Here is a snippet on how it is done.The file can be found at <TivaWare_Installation/boot_loader. The flash controller has the prefetch feature. It will prefetch 256 bits at a time. The prefetch buffers allow the maximum performance of a 120 MHz CPU speed to be maintained with linear code or loops that fit within the prefetch buffer. So from performance stand point, I don't see much difference between VTABLE in flash or in RAM unless you are trying to create a boot loader where you might need to erase the first flash sector in which the VTABLE resides.

ProcessorInit: .asmfunc
    ;;
    ;; Copy the code image from flash to SRAM.
    ;;
    movs    r0, #0x0000
    movs    r1, #0x0000
    movt    r1, #0x2000
    ldr     r2, bss_start
copy_loop:
        ldr     r3, [r0], #4
        str     r3, [r1], #4
        cmp     r1, r2
        blt     copy_loop

    ;;
    ;; Zero fill the .bss section.
    ;;
    movs    r0, #0x0000
    ldr     r2, bss_end
zero_loop:
        str     r0, [r1], #4
        cmp     r1, r2
        blt     zero_loop

    ;;
    ;; Set the vector table pointer to the beginning of SRAM.
    ;;
    movw    r0, #(NVIC_VTABLE & 0xffff)
    movt    r0, #(NVIC_VTABLE >> 16)
    movs    r1, #0x0000
    movt    r1, #0x2000
    str     r1, [r0]

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CCS/TM4C129ENCPDT: TM4C129ENCPDT ISR from RAM