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Original question:

TMS570LS0432: Understanding the initialization routine

TMS570LS0432: Understanding the initialization routine

_MM_
Expert 1995 points
Part Number: TMS570LS0432
Other Parts Discussed in Thread: HALCOGEN

The initialization sequence of the TMS570LS04x/03x (SPNA163) points to the check of any ESM group3 error, and actually the corresponding source code generated by HALcoGen is:

/* Check if there were ESM group3 errors during power-up.
     * These could occur during eFuse auto-load or during reads from flash OTP
     * during power-up. Device operation is not reliable and not recommended
     * in this case.
     * An ESM group3 error only drives the nERROR pin low. An external circuit
     * that monitors the nERROR pin must take the appropriate action to ensure that
     * the system is placed in a safe state, as determined by the application.
     */
    if ((esmREG->SR1[2]) != 0U)
    {
/* USER CODE BEGIN (24) */
/* USER CODE END */
    /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
    /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
        for(;;)
        { 
        }/* Wait */                 
/* USER CODE BEGIN (25) */
/* USER CODE END */
    }

Nevertheless, the group 3 of ESM is not available for selection in Halcogen. Anyway, it checks the group 2 (!!!) only. Can somebody help me to understand how is checking against ESM error group 3?

Thanks ahead.

  • 0
    TI__Mastermind 21425 points

    Hello Marco,
    You should add code for checking ESM group3. ESM Group3 channels has no interrupt generation and nERROR pin has predefined behavior and are high-severity . Only four error sources are mapped to group3 (take a look at datasheet so see mapped channels).

    Best regards,
    Miro

  • 0 in reply to Miro
    Expert 1995 points

    Hi Miro,

    Thanks for you explanation, but maybe the question was not really clear: both, the comment on the code and the description of the initialization aim to check any presence of group3 errors, but actually what the code does at that point is just checking against group2 of errors. Indeed, in the register definition (reg_esm.h file) you can find that the SR1[2] is actually the status register for the group 2 and not 3. Why not checking SR1[3], instead ?

    I hope to have been clearer now and thanks ahead for a reply.

  • 0 in reply to _MM_
    TI__Mastermind 21425 points
    Hi Marco,
    This code checks only group2! In same way group3 could be checked. I'll forward this to my colleagues for clarifications in comments.

    Best regards,
    Miro
  • 0 in reply to Miro
    Expert 1995 points
    Hi Miro,
    Thanks for the quick reply.
    Please, let me know if it is intentional or it is actually a mistake after the discussion with your colleagues. Thanks ahead.
  • 0
    TI__Mastermind 49120 points
    The SR1 array is defined as an array of three 32-bit registers, which include the addresses 0x18 (ESMSR1), 0x1C (ESMSR2)and 0x20 (ESMSR3).

    This way the index 2 of the array actually refers to the group3 status flags.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Expert 1995 points

    Thanks Sunil for the finding. I temporary forgot that in C there is also the item 0 to count.

    Other question about the initialization. At the PLL setup, the parameter MASK_SLIP (bit 30-29 of PLLCTL1 at offset=70h) is set to 'All other values' to bypass PLL Slips, isn't it? I am asking because it is not specified in the document regarding the standard initialization of this MCU (SPNA163). Attach the code below.

    systemREG1->PLLCTL1 =  (uint32)0x00000000U
                        |  (uint32)0x20000000U // <---question
                        |  (uint32)((uint32)0x1FU << 24U)
                        |  (uint32)0x00000000U
                        |  (uint32)((uint32)(6U - 1U)<< 16U)
                        |  (uint32)(0x7700U);

  • 0 in reply to _MM_
    TI__Mastermind 21425 points
    Hi Marco,
    MASK_SLIP = 10 ignores a PLL slip condition flagged by the FMPLL macro.
    Writing any other value to MASK_SLIP causes the FMPLL to be bypassed so that the OSCIN is used as the output from the FMPLL macro.
    If you use HALCoGen to generate this file, you can uncheck "Bypass on PLL Slip" under PLL tab and then the value will be (uint32)0x40000000U.
    Best regards,
    Miro