RM48L930: Hercules SDK SDRAM not working

Keith

Part Number: RM48L930
Other Parts Discussed in Thread: HALCOGEN, RM48L952

Support Path: /Product/Help with Device Selection/

Hello,

I am trying to enable the 8 MB of SDRAM on the Hercules HDK board. The HDK board contains a ISSI IS42S16400 SDRAM (1 MBit x 16 x 4 banks). I have read several similar older posts and have tried the following setup that is still not working:

1. in Halcogen, in the PINMUX tab, I checked the ENABLE_EMIF_CLK output

2. in Halcogen EMIF tab, enabled EMIF_SDRAM. I also unchecked the EMIF Async1-3 boxes.

3. in Halcogen EMIF SDRAM tab, I set the following:

t(rc) = 64; t(rp) = 21; t(rcd) = 21; t(wr) = 11; t(ras) = 43; t(rc) = 64; t(rrd) = 15; t(xsr) = 71; refresh period = 60; refresh cycles = 4096; CAS latency = 3; banks = 4;

pagesize = 256; SDRAM init time = 200

4. My CPU is running at a slow 40 MHz. (HCLK = GCLK = VCLK1 = VCLK2 = VCLK3 = 40 MHz)

5. I verified when running that GPREG1 bit 31 = 1

6. In Halcogen R4-MPU-PMU tab, Region 6 is enabled at SDRAM base address 0x80000000, size = 8 MB. Type = STRONGLY_ORDERED_SHARABLE, and Permisssion = PRIV_RW_USER_RW_EXEC

My code is running from flash memory and uses on-chip RAM at 0x0800_0000. As a test, in the debugger I stop execution and open a memory window to address SDRAM at 0x80000000 but see all ?????????. I cannot set or modify the memory at the SDRAM address.

Note, previously I tried editing the sys_link.cmd file and added a SDRAM (RW) memory definition at location 0x80000000, length 0x800000, then pointed the .sysmem section to use SDRAM. But when my code tried to malloc memory I got a data abort. So I reverted that change and just try to peek and poke memory in the debugger at location 0x80000000. (which appears as non-present memory indicated by 'question marks' (????????)

Can you suggest what is needed to get SDRAM working on the Hercules RM48 HDK board?

thanks,

Keith

over 7 years ago

0 Keith over 7 years ago

Intellectual 800 points

Hello,

My Hercules HDK board SDRAM is still not working. I used an oscilloscope to verify that the SDRAM clock signal is present, with frequency = 40 MHz as expected.

Is there anyone at TI that can help me with this problem?

thank you,

Keith

0 Sunil Oak over 7 years ago in reply to Keith

TI__Mastermind 49120 points

Keith,

Which CCS version are you using? It appears to be an issue with the memory configuration defined for the debugger. Can you check the .gel file that is loaded by default for the part that you define the code project for (RM48L930)?

As for the abort while configuring SDRAM, can you check whether this SDRAM region is configured to be read/writable in the CPU's MPU settings?

Regards,
Sunil

0 Keith over 7 years ago in reply to Sunil Oak

Intellectual 800 points

Sunil,

I am using CCS v7.4. In HalcoGen, Region 6 is enabled as shown below. I'm not familiar with the .gel file, what is it used for, and where do I look for it?

thanks,

0 Sunil Oak over 7 years ago in reply to Keith

TI__Mastermind 49120 points

Keith,

There is a file called rm48l930.gel under the C:\ti\ccsv8\ccs_base\emulation\gel folder. This has the memory map that is used by the debugger when you define a CCS project for the RM48L930 part.

It looks like this:
GEL_MapAdd(0x60000000, 0, 0x10000000, 1, 1); /* External Async Memory */
GEL_MapAdd(0x80000000, 0, 0x08000000, 1, 1); /* External Sync SDRAM Memory */

Can you confirm if you have these lines in the .gel file used with CCS v7.4?

Regards,
Sunil

0 Keith over 7 years ago in reply to Sunil Oak

Intellectual 800 points

Yes, those lines are present in the rm48l952.gel file's memmap() function shown below. I also attached a screenshot of my targetConfig settings.

/*----------------------------------------------------------------------------*/

/* Function - memmap(memSel, extMem) */

/* */

memmap(memSel, extMem){

GEL_MapOff();

GEL_MapReset();

/* Flash / RAM Definition */

if(memSel == FLASH){

/* Flash Definition */

GEL_MapAdd(0x00000000, 0, 0x00300000, 1, 0); /* Internal Flash () */

GEL_MapAddStr(0xF0400000, 0, 0x00060000, "R|AS2", 0); /* Internal Flash ECC */

GEL_MapAdd(0x08000000, 0, 0x00040000, 1, 1); /* Internal RAM */

GEL_MapAdd(0x08400000, 0, 0x00040000, 1, 1); /* Internal RAM ECC */

GEL_MapAdd(0x20000000, 0, 0x00300000, 1, 0); /* Mirrored Flash */

GEL_MapAdd(0xFE000000, 0, 0x01000000, 1, 1); /* CRC/PSA */

}

if(memSel == RAM){

/* RAM Definition */

GEL_MapAdd(0x00000000, 0, 0x00040000, 1, 1); /* Internal RAM */

GEL_MapAdd(0x00400000, 0, 0x00040000, 1, 1); /* Internal RAM ECC */

GEL_MapAdd(0x08000000, 0, 0x00300000, 1, 0); /* Internal Flash () */

GEL_MapAddStr(0xF0400000, 0, 0x00060000, "R|AS2", 0); /* Internal Flash ECC */

GEL_MapAdd(0x20000000, 0, 0x00300000, 1, 0); /* Mirrored Flash */

GEL_MapAdd(0xFE000000, 0, 0x01000000, 1, 1); /* CRC/PSA */

}

if(extMem == EMIF){

GEL_MapAdd(0x60000000, 0, 0x10000000, 1, 1); /* External Async Memory */

GEL_MapAdd(0x80000000, 0, 0x08000000, 1, 1); /* External Sync SDRAM Memory */

}

0 Keith over 7 years ago in reply to Keith

Intellectual 800 points

Sunil,

Would you be able to send me a working project for the Hercules RM48 HDK board, that has SDRAM enabled and working? (including the Halcogen config?) I am running all clocks at 40 MHz to save power, so VCLK3 (=SDRAM clock) = 40 MHz.

In HalcoGen, can you check my EMIF SDRAM settings for a 40 MHz SDRAM clock? They are:

trc = 63

trp = 20

trcd = 20

twr = 50 nS (= 2 clk period)

tras = 42

trc = 63

trrd = 14

txsr = 70

refresh period = 64 mS

refresh cycles = 4096

CAS latency = 3

banks = 4

pagesize = 256

SDRAM init time = 200 uS

thanks,

Keith

0 Keith over 7 years ago in reply to Keith

Intellectual 800 points

Hello,

Is any more help from TI available to get SDRAM working on the Hercules HDK board? My project is on hold until SDRAM is working.

thanks,

Keith

0 Sunil Oak over 7 years ago in reply to Keith

TI__Mastermind 49120 points

7824.RM48 HDK SDRAM Test.zip

Keith,

I am attaching a zipped file that includes a CCS project that tests the SDRAM on the HDK. You can use this as a reference for your code.

Regards,

Sunil

0 Keith over 7 years ago in reply to Sunil Oak

Intellectual 800 points

Thanks Sunil. I built your project and the SDRAM works on my board. But your project contains files not generated by HalCoGen. Example, it contains emif.h, emif_config.c, and emif_config.h, and main() calls emif_init().

I will merge these files and test the results. But can you provide a SDRAM-enabled project where the BSP (and the emif code) was created by HalCoGen?

thanks,

0 Sunil Oak over 7 years ago in reply to Keith

TI__Mastermind 49120 points

Keith,

emif.h only contains the control and status registers for the EMIF. This is generated by HALCoGen.

emif_config.c and emif_config.h are additional files that contain the C function definitions and declarations that are used in the test program. These can be replaced by your application, or can even be included as part of the sys_main.c file. As you can see the main() routine does nothing but call the EMIF test routine.

0 Keith over 7 years ago in reply to Sunil Oak

Intellectual 800 points

Sunil,
I merged the emif_config.c and .h files from your bare-metal project into my FreeRTOS-based app, and replaced the call to emif_SDRAM_StartupInit() in system.c with a call to your emifInit(). The SDRAM is working now inside my main program, before the FreeRTOS call to vTaskStartScheduler(). In xPortStartScheduler() FreeRTOS enables the MPU and when that happens my SDRAM mapped at location 0x80000000 becomes invalid and further accesses to this region cause a data abort.

Per this link :
e2e.ti.com/.../660420

I added this call inside of prvSetupDefaultMPU():
prvMpuSetRegion(portFIRST_CONFIGURABLE_REGION, 0x80000000, portMPU_SIZE_8MB | portMPU_REGION_ENABLE, portMPU_PRIV_RW_USER_RO_EXEC | portMPU_STRONGLYORDERED_SHAREABLE);

But at the end of xPortStartScheduler() the code calls vPortStartFirstTask() and the MPU settings are lost and further SDRAM accesses cause a data abort. Here is the asm code for vPortStartFirstTask, can you tell me what is needed so that portRESTORE_CONTEXT does not lose the MPU SDRAM region setup?

; Start the first task by restoring its context.
.def vPortStartFirstTask
.asmfunc vPortStartFirstTask
cps #0x13
portRESTORE_CONTEXT
.endasmfunc

Thanks,

0 Sunil Oak over 7 years ago in reply to Keith

TI__Mastermind 49120 points

Keith,

The region number defined as portFIRST_CONFIGURABLE_REGION may be originally mapped to some other memory region by HALCoGen. It is better to explicitly define a region for the SDRAM as done in the example you cited (match the region number with the one generated by HALCoGen code):

prvMpuSetRegion(portPRIVILEGED_SDRAM_REGION, 0x80000000, portMPU_SIZE_32MB | portMPU_REGION_ENABLE, portMPU_PRIV_RW_USER_RO_EXEC | portMPU_STRONGLYORDERED_SHAREABLE);

Check out this application note for more details:
www.ti.com/.../spna177.pdf

The pdf document even has a link to download a demo CCS project that explains the details.

Regards,
Sunil

0 Keith over 7 years ago in reply to Sunil Oak

Intellectual 800 points

Sunil,
In my HalCoGen setup, the 6th MPU region (Region 6) is SDRAM, at location 0x80000000, size = 8 MB. That corresponds to portFIRST_CONFIGURABLE_REGION = 5. So my settings should be Ok. Any other ideas? HalCoGen has a switch to let me disable the MPU, but I think I would have to modify a lot of the code in portASM.asm and port.c if I disable it. Thoughts?

0 Sunil Oak over 7 years ago in reply to Keith

TI__Mastermind 49120 points

Keith,

See this post about external memory accesses with FreeRTOS. This post also has a link to a note from FreeRTOS explaining the use of the MPU.

e2e.ti.com/.../323853

Regards,
Sunil

0 Keith over 7 years ago in reply to Sunil Oak

Intellectual 800 points

Thanks Sunil, that is very helpful!

Regards,

Keith

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RM48L930: Hercules SDK SDRAM not working