TMS570 A to D operation and parameters

Hello William,

See comments embedded in your post below:

Are there additional AC and DC specifications available such as SINAD, SNR, ENOB, AC timing diagrams etc?

The current datasheet and Technical reference does not contain these specifications. 

>> There are no current plans to include more AC and DC specifications in the datasheet. The 12-bit ADC on the TMS570LS202016 has a typical ENOB of 10.9. Note that this value is not characterized and is only a typical number.

The leakage current is specifed for I(ail) leakage current per pin of -200 to 200nA.

In figure 7.17.4 (MibADC input model) shows leakage current for each of the inputs on the ADC side of the MUX switch.
Are these currents summed to calculate the total leakage current of the active pin?

>> Yes, the total leakage current when a conversion is ongoing is the sum of the individual pin leakage currents for the remaining pins.

Perhaps this is just a definitions question about the relationship between groups and the two ADC cores 1 and 2:

The documentation states that the ADC module can service one group at a time.  When calculating group cycle time does
the group cycle time count the acquisition of the input channel [X] for ADC1 then input channel [x] for ADC2 or do the two
ADC cores operate concurrently where the group cycle time is counted for each ADC core?  Of perhaps someone has some info
on the timing relationships between the two ADC cores?

>> The two ADC cores operate independently. They only share 8 input channels between them. That is, there are 8 channels that can be converted using ADC1, or ADC2, or both. The timings for both ADC cores must be configured independently by the application.

The group cycle time for ADC1 is independent of the group cycle time for ADC2. There are some group conversion trigger options that are common between the two ADC cores. This allows the application to synchronize the start of conversion for the two ADC cores.

Regards,

Sunil

Thank you Sunil for your answers to my previous questions.  If possible I would like to clarify some issues in evaluating the ADC input circuit.

I had some more questions on how to determine leakage current for the TMS570LS20216 (QFP) ADC inputs.

When the ADC input is switched on by the multiplexer what would be the total calculated leakage current?

Given that there are 24 total ADC inputs, and if the active input does not have leakage current.
Would the active input "see" 23 * the AIL rating of 200nA?

Are all of the inputs on the same muliplexed bus to the two ADC cores?
The diagrams in the datasheets show the relationship of the inputs to one of the ADC cores but do not show the relationship between
the dedicated inputs, the shared inputs and the two cores.

Is the leakage current applied for only mux switches that are off?
The diagram does not show leakage current for the on device.

Is there a difference in total leakage current between the BGE and QFP devices

i.e. the number of pins bonded out on the two devices are different, does this affect total leakage current?

The leakage current is depicted as a current source, is the leakage current voltage independant?

Best Regards,

Will Stanton