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TMS570LS3137: Can one software-interrupt preempt another software interrupt?

jimj2713
Expert 2385 points

Part Number: TMS570LS3137

My system requires 3 interrupts with different frequencies and priorities. I have a 20Khz ISR bound to the FIQ, and a 5Khz ISR is generated via the software-interrupt using the IRQ (and can be preempted by the FIQ). I would like to create a third interrupt running at 100Hz that could be preempted by either the 5Khz or 20Khz interrupts. I think the answer here is no, but I need to be sure because the work-around to this is much work.

Thanks,

Jim

  • 0
    TI__Mastermind 49120 points
    Hi Jim,

    IRQ and FIQ are the two levels of interrupts that the CPU distinguishes, with FIQ being able to preempt the IRQ. So your system would work perfectly if there were only two interrupts required. For your current problem you can configure multiple compare interrupts (up to 4) from the RTI (for 20KHz FIQ, 5KHz IRQ, and 100Hz IRQ). 20KHz FIQ will preempt both the 5KHz and 100Hz IRQ interrupts. The 5KHz IRQ ISR can check for the higher-priority interrupt multiple times within the ISR (if the ISR execution time is longer than x us).

    I don't understand what you mean by "generated via the software-interrupt".

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Expert 2385 points

    Sunil,

    The Software Interrupt I referred to was the SSIR1 register. 

    In the scheme you described above, if the lower-priority/100Hz interrupt was executing, and it was time for the higher-priority/5Khz interrupt to occur, wouldn't the 100Hz-ISR interrupt have to finish first (because they are both in the same IRQ context)?

    Thanks,

    Jim

  • 0 in reply to jimj2713
    TI__Mastermind 49120 points
    Jim,

    Yes, the 100Hz interrupt service routine needs to check periodically if there is a flag already set for the 5KHz interrupt request (within the RTI interrupt flag register). If it gets this interrupt while the ISR is still not completed, then it could service both the 5KHz and the 100Hz interrupts within the same ISR without exiting and re-entering a different ISR. So you would essentially be doing a software-based preemption of the 100Hz interrupt.

    Regards,
    Sunil